• Design Verification Engineer

    Meta (Austin, TX)


    Summary:

    Reality Labs focuses on delivering Meta's vision through AI-first devices that leverage our wearable technologies. The compute performance and power efficiency requirements require custom silicon. We are driving the state-of-the-art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable Meta’s Wearable devices that blend our real and virtual worlds throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.

    Required Skills:

    Design Verification Engineer Responsibilities:

    1. Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification

    2. Develop functional tests based on verification test plan

    3. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage

    4. Debug, root-cause and resolve functional failures in the design, partnering with the Design team

    5. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality

    6. Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

    Minimum Qualifications:

    Minimum Qualifications:

    7. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

    8. 6+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification

    9. 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies

    10. Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

    Preferred Qualifications:

    Preferred Qualifications:

    11. Experience with revision control systems like Mercurial(Hg), Git or SVN

    12. Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

    13. Experience in development of Universal Verification Methodology (UVM) based verification environments from scratch

    14. Experience in one or more of the following areas: SystemVerilog Assertions (SVA), Formal, and Emulation

    15. Prior working knowledge of Audio/image/Video processing compute intensive cores

    Public Compensation:

    $142,000/year to $203,000/year + bonus + equity + benefits

    **Industry:** Internet

    Equal Opportunity:

    Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

     

    Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [email protected].