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Asic Manager, Design Verification
- Meta (Sunnyvale, CA)
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Summary:
Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. To apply, click “Apply to Job” online on this web page.
Required Skills:
Asic Manager, Design Verification Responsibilities:
1. Work with researchers and architects defining verification plans for each of the different core IP.
2. Define and track detailed test plans for the different modules and top levels.
3. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
4. Debug, root-cause and resolve functional failures in the design, partnering with the Design team.
5. Collaborate with cross-functional teams including Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
6. Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.
7. Provide technical mentorship, plan work assignments, and manage performance reviews for design verification engineers on the team.
Minimum Qualifications:
Minimum Qualifications:
8. Requires a Master's degree (or foreign degree equivalent) in Computer Science, Engineering, Information Systems, Analytics, Mathematics, Physics, Applied Sciences, or a related field and 5 years of experience in the job offered or in a computer-related occupation.
9. Requires 5 years of experience in the following:
10. 1. Experience in HDL language (System Verilog, or Verilog), and scripting language (TCL, Python, Perl, or Shell-scripting)
11. 2. Design Verification in Verification methodologies (UVM or OVM) creating test plans, constrained random verification, Functional Coverage development
12. 3. Experience in C/C++/SystemC for Bit Accurate and Transaction Accurate Modeling etc.
13. 4. Skills to Architect UVM-based reusable test benches with components for stimulus, checkers, and reference models and
14. 5. Experience in block/IP/SoC/full chip level verification.
Public Compensation:
$272,316/year to $287,650/year + bonus + equity + benefits
**Industry:** Internet
Equal Opportunity:
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [email protected].
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