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The application window is expected to close on 6/15/2025

This is an onsite role with a strong preference working out of the Maynard, MA office location, but can also be based out of our San Jose, CA or RTP, NC offices.

Meet the Team:

Acacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs, and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross-functional experts capable of solving the challenges of next-generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world’s best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all.

Your Impact:

As part of a growing Design Verification Team, you will work with other verification, DSP, and RTL engineers to ensure successful verification of complex ASICs throughout its pre-silicon lifecycle. You will work with C++ and UVM building test-benches and gathering and analyzing coverage reports. Responsibilities include:

* Develop detailed and comprehensive test plans.

* Develop verification test benches at block, inter-block, and chip levels.

* Apply innovative verification techniques to complex designs.

* Participate in the review of design verification coding and coverage metrics.

* Work collaboratively with the team to develop & incorporate the latest test technologies & processes.

Minimum Qualifications:

* Bachelor's degree and 5+ years of experience, or a Master's degree and 3+ years majoring in Computer Science, Computer Engineering, or Electronic/Electrical Engineering.

* Demonstrated experience in ASIC design verification methodologies and flows.

* Experience with C++ model co-simulation.

* Experience with HVL and HDL languages and tools, scripting and programming languages Verilog, System Verilog, C++, Perl and/or Python.

Preferred Qualifications:

* UVM experience is a plus

* Strong problem solving, communication, and team skills.

* Experience in object oriented programming.

* Networking knowledge is preferred, but not essential.

#WeAreCisco

#WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all.

Our passion is connection—we celebrate our employees’ diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage.

Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best.

We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer—80 hours each year—allows us to give back to causes we are passionate about, and nearly 86% do!

Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!

Cisco is an Affirmative Action and Equal Opportunity Employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis.

Cisco will consider for employment, on a case by case basis, qualified applicants with arrest and conviction records.