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Job Description

Collaborate with a small team of digital engineers to design, implement, and test VHDL for a new ASIC to be used in new test and measurement products.

Collaborate with driver software teams to align on functional requirements.

Develop register maps and generate documentation to ensure clear design intent to the broader project team.

Own the full FPGA design, including logic implementation, data movement and analysis, testbenches, compilation, and timing analysis.

Develop and execute plans for logic validation using an FPGA prototype test board.

Be the voice of your digital design ownership in project meetings by estimating level of effort for design tasks, providing input on status of work, and proactively raising technical concerns.

We are a company committed to creating inclusive environments where people can bring their full, authentic selves to work every day. We are an equal opportunity employer that believes everyone matters. Qualified candidates will receive consideration for employment opportunities without regard to race, religion, sex, age, marital status, national origin, sexual orientation, citizenship status, disability, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or recruiting process, please send a request to [email protected] . The EEOC "Know Your Rights" Poster is available here (https://www.eeoc.gov/sites/default/files/2023-06/22-088\_EEOC\_KnowYourRights6.12ScreenRdr.pdf) .

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Skills and Requirements

Minimum Bachelor's degree in Electrical, Computer, or Software Engineering, or a related discipline.

Minimum 7+ years relevant engineering experience in digital hardware design.

Experience using VHDL to implement synthesizable logic targeting FPGAs.

Experience with static timing analysis and writing timing constraints.

Experience using synthesis tools and achieving timing closure.

Experience writing testbenches and simulation models to verify logic designs.

Experience defining feature requirements in collaboration with software teams.

Familiar with common clock domain crossing methods.

Ability to adapt quickly to established custom VHDL workflow tools, VHDL coding conventions, code review policies, and code quality requirements.

Located within a commutable distance to NIs offices in Austin, TX, or willing to relocate. Experience SystemVerilog to implement synthesizable logic targeting FPGAs.

Experience writing RTL for ASIC projects.

Experience with gate-level simulation and debug.

Experience bringing up prototype hardware.

Experience with high-speed digital design

Familiar with board level signal integrity simulation tools.

Familiar with AMD (Xilinx) FPGAs and CPLDs, as well as their design tools.

Experience collaborating with other technical disciplines such as Analog, Mechanical, and RF. null

We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal employment opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment without regard to race, color, ethnicity, religion,sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military oruniformed service member status, or any other status or characteristic protected by applicable laws, regulations, andordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request to [email protected].