• Senior E/E & Semiconductor Engineer - CAD/EDA…

    Capgemini (San Francisco, CA)


    Job Summary:

    We are seeking a skilled CAD Infrastructure engineer to support our ASIC design team. The ideal candidate will be responsible for developing and maintaining the CAD infrastructure, ensuring efficient design workflows, and supporting the design and verification of ASICs.

    Required Skills:

    • Languages: shell scripting Python 3.x

    • Revision control: CI/CD

    • Tool knowledge: ASIC tool knowledge

    • Linux Shell scripting

    • Knowledge of industry standards and best practices in ASIC design.

    • This role is crucial for ensuring the efficiency and effectiveness of the ASIC design process, making it an integral part of the engineering team

    Qualifications:

    • **Education:** Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

    • **Experience:** Proven experience in CAD tool development and support, preferably in an ASIC design environment.

    • **Technical Skills:** Proficiency in CAD tools (e.g., Cadence, Synopsys), scripting languages (e.g., Python, Perl), and EDA tool integration.

    • **Problem-Solving:** Strong analytical and problem-solving skills.

    • Outstanding analytical and problem-solving skills.

    • Always eager to learn and improve.

    • Strong interpersonal and writing skills.

    **Job:** _Developer_

    **Organization:** _ERD PPL US_

    **Title:** _Senior E/E & Semiconductor Engineer - CAD/EDA – Silicon Design/Verification Infrastructure Engineer_

    **Location:** _CA-San Francisco_

    **Requisition ID:** _078199_