"Alerted.org

Other Professional

**Principal PCB & Substrate Layout Engineer** Phoenix, AZ Posted: 5/7/2025

Job Description

Job ID#:

211179

Job Category:

Other Professional

Position Type:

Associate - W2

Shift:

1

PDS Defense, Inc. is seeking a Principal PCB & Substrate Layout Engineer, in Phoenix, AZ. Job ID#211179

Job Description:

Seeking an experienced Principal PCB & Substrate Layout Engineer to join our growing, engaging, and collaborative team. As a valued team member, you will collaborate to deliver leading edge microelectronics that are game changing and impactful to our nation's defense.

The successful candidate wants to be part of a dynamic team that is transforming our business and the defense-grade microelectronics industry while executing on near-term program commitments while fostering a culture of teamwork and agility.

You are responsible for:

Providing technical leadership to the engineering team specifically focused on High-Speed Interfaces and High Density Substrates layout techniques and understanding and improving our layout development processes to ensure we produce quality products using your expertise in PCB and Substrate layout engineering.

Responsibilities:

* Driving design, layout, and analysis of complicated electrical and mechanical systems and their constituent parts including: high-density interposers, substrates, and printed circuit board (PCB) layouts. This includes power, digital, analog, and RF signals across multiple die (primarily flip-chip)

* Hands on high-speed, multi-layer packaging, high-density interconnects (HDI), blind and buried vias, ball grid arrays (BGAs), RF, design for test (DFT), impedance calculations, cross talk, differential pairs, PCB stack-ups, PCB via structures, electromagnetic compatibility (EMC), material studies/selection, etc.

* Understand Design For Manufacturing rules of our suppliers and ensure design process matches their capabilities

* Understand and provide fabrication drawings that match the intent of the design and support the fabrication suppliers to ensure the technical intent is transferred successfully

* Support package material characterization frequency dependent model; skin effects, smoothness, roughness, dielectric loss and dielectric constant

* Work with peers and the engineering team to review the artwork and drawings at different stages and at the final design review for fabrication and assembly

* Provide support for multidisciplinary investigations and feasibility studies with collaboration across engineering disciplines

* Provide Technical guidance for interfacing to customers, subcontractors, assemblers, fabricators, and vendors/suppliers, operations, quality, supply chain, and supporting organizations

* Works on complex issues where analysis of situations or data requires an in-depth evaluation of variable factors

* Considers the effects of actions on the system as a whole, i.e. 'systems-thinking'

* Willing to help the team in areas outside of specific technical discipline to accomplish goals

You will be a part of:

The team responsible for the rapid development of affordable, chip-scale, secure, open system architecture devices. This leading-edge capability also addresses a need by the Department of Defense (DoD) for made-in-USA microelectronics that equip our warfighters with state-of-the-art, Trusted, military-grade products that leverage the most advanced commercial technologies..

To succeed in this role, you should have the following skills and experience:

* Minimum Education: Bachelor's Degree in Engineering or equivalent education and experience required

* Minimum Experience: 10+ years as a PCB and/or High-Density Package Layout designer using industry standard layout tools like Cadence APD* Experience with APD+ physical and electrical constraint editor

* HDI stack-ups, including use of blind & buried micro-vias, specialty RF dielectric materials, and trace width/spacing around 15um/15um down to 2um/2um or below

* Experience with 2.5D devices, interposer or substrate design, flip-chip, surface mount, die stacking, package stacking, substrate stacking and other techniques

* Experience using a Cadence schematic / netlist driven CAD layout process, e.g. Cadence APD+ (Allegro) and supporting tools

* High-end FPGA package or board design experience

* Ability to work with our Mechanical team to design full 3D models for fit checks and thermal

* Understanding of layout techniques in Digital, Analog, and/or RF layouts

* Knowledge of electronic packaging techniques

* Experience using a CAM package for manufacturing data validation. Knowledge of CAM350 & Blueprint is preferred

* Working knowledge of JEDEC /IPC design, fabrication, and assembly specifications

* Experience creating assembly documentation and fabrication deliverables per company and industry standards

* Must be a US Person

* Work effectively individually and as part of a team

* Embrace the company culture that includes the following values and behaviors:

o Teamwork, execution, and communication

Benefits offered to vary by the contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.

Job Requirements

Minimum Security Clearance:

No Clearance

VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled

To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit http://www.tadpgs.com/candidate-privacy/ or https://pdsdefense.com/candidate-privacy/

The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:

+ The California Fair Chance Act

+ Los Angeles City Fair Chance Ordinance

+ Los Angeles County Fair Chance Ordinance for Employers

+ San Francisco Fair Chance Ordinance

VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled