• FPGA/Firmware Design Engineer

    TAD PGS, Inc. (San Diego, CA)


    We have an outstanding Contract position for anFPGA/Firmware Design Engineerto join a leading Company located in theSan Diego, CAsurrounding area.

     

    Pay Rate: $120.48

     

    US Citizenship is required.

     

    Candidate must have the ability to obtain and maintain a Secret Security Clearance.

     

    The FPGA/Firmware design engineer's primary job functions include designing, implementing, and testing firmware solutions targeting unique high-speed FPGAs and their supporting circuitry.

    Responsibilities :

    + Collaborate with a multidisciplinary design team (electrical engineers, systems engineers, and scientists) to implement and integrate FPGA designs and sensor systems.

    + Analyze, design, simulate, and implement algorithms in hardware descriptor languages, HDL (VHDL, Verilog), based on MATLAB model(s).

    + Analyze, design, and implement HDL test benches in hardware description languages, HDL (VHDL, Verilog), for code validation and validation against models.

    + Analyze schematic diagrams for either custom or commercial-off-the-shelf (COTS) electronic hardware involving high-speed digital and/or analog circuitry in associated FPGA-centric systems.

    + Conduct experimental tests on the latest FPGA and SoC evaluation boards, evaluate results, and then develop specifications for selecting next-generation components for deliverable systems.

    + Work on problems of diverse scope, determining methods and procedures to be used on new assignments, and providing feedback and recommendations to other technical personnel.

    + Develop project test plans and test procedures, provide test planning support, and assist in the execution of both lab testing and field testing.

    + Develop and maintain requirements documents, functional specification documents, interface control documents, etc.

    Basic Hiring Criteria :

    + Bachelor's degree in Electrical or Computer Engineering with 8-12 years of relevant experience.

    + Experience with, and understanding of, FPGA system design and testing.

    + Experience with embedded Software/Firmware design.

    + Experience with C/C++, and MATLAB.

    + Understanding of multiple high-speed serial communication standards and interfaces (e.g. Aurora, 10Ge, PCIe, DDR4/3/2/1, JESD204B)

    + Experienced with version control systems including SVN and Git.

    + Hands-on laboratory experience with instrumentation, test equipment, and debug/test methods.

    + Candidate must be a US Citizen and possess (and be able to maintain) a Final DoD Secret Clearance.

    Desired Qualifications :

    + Master's (MS) degree in Engineering discipline.

    + Familiarity with modern Xilinx FPGA families and design tools (7-series FPGAs, Ultrascale+, Vivado, Xilinx IP cores).

    + Experience working with SoC designs such as Zynq and Zynq Ultrascale+ including architecting and interfacing with peripherals, interrupts, and related bus architectures.

    + Experience developing and implementing FPGA-optimized versions of DSP algorithms (e.g., modulation/demodulation, PLLs, filters, image processing).

    + Experience with standard internal interfaces such as AXI4, AXI4-Stream, and AXI4-Lite.

    + Experience working with embedded operating systems (i.e., RTOS such as Green Hills).

     

    Benefits offered to vary by the contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.

     

    VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled

     

    To read our Candidate Privacy Information Statement, which explains how we will use your information, please visithttp://www.tadpgs.com/candidate-privacy/orhttps://pdsdefense.com/candidate-privacy/

    The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:

    + The California Fair Chance Act

    + Los Angeles City Fair Chance Ordinance

    + Los Angeles County Fair Chance Ordinance for Employers

    + San Francisco Fair Chance Ordinance