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Minimum qualifications:

+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

+ 3 years of experience in analog design, integration, or validation.

+ Experience designing or integrating analog physical interface (PHY) designs (e.g., PCIe, UCIe, or HBM PHYs).

+ Experience with design integration flows and requirements.

Preferred qualifications:

+ Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.

+ Experience in writing design specifications.

+ Experience in coordinating designs through the entire silicon product lifecycle.

+ Ability to coordinate and execute across multiple cross-functional teams.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As part of the Tensor Processing Unit (TPU) interface design team, you will play a pivotal role in pushing the boundaries of technology to improve the performance and power of our TPUs. You will drive the selection, integration, and execution of our high speed IO Design

Intellectual Propertys (IP). In this highly cross-functional role, you will be tasked with specifying and meeting the technical requirements and coordinating all aspects of the IP integration across all phases of the silicon lifecycle.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google (https://careers.google.com/benefits/) .

+ Contribute to PHY IP selection and procurement.

+ Inform PHY IP planning and roadmap definition.

+ Drive pre-silicon integration of PHY Design IPs.

+ Coordinate PHY IP requirements with cross-functional teams (e.g., Design, Verification, Physical Design, DFT, and Post-Silicon).

+ Assist in post silicon bring-up and validation of PHY IP designs.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.