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Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the **Compute** **Silicon and Manufacturing** **Organization** (CSME) team is instrumental in defining and delivering operational measures of success for the Cobalt program through hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. CSME is at the forefront of innovation and application of AI to silicon development workflows. We are looking for senior engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a **Senior DDR Subsystem Verification Engineer** to join the team.

Responsibilities

+ Own or lead verification of one or more aspects/features of a memory controller Intellectual Property (IP) and/or Double Data Rate (DDR) subsystem integration with Physical Layer (PHY)

+ Learn about the design and interact with partner teams to define verification strategies and test plans

+ Develop verification environments and run and debug simulations to drive quality

+ Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals

+ Innovate to improve verification efficiency through methodologies or tools

+ Apply industry leading generative AI solutions to verification work

+ Coach and mentor others in your areas of expertise

+ Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion

Qualifications

Required Qualifications:

+ Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience

+ OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience

+ OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.

+ 4+ years of pre-silicon subsystem or IP verification experience.

+ 3+ years of DDR subsystem verification experience.

+ 1+ years of DDR PHY intergrating or verifying experience

Other Qualifications

+ Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications

+ Demonstrated experience in verifying memory controller, DDR PHY, and/or at DDR sub-system level including integration verification of memory controller IP with DDR PHY and Electronic Design Automation (EDA) vendor sourced Dual In-line Memory Module (DIMM) Verification IP (VIP)

+ Deep understanding of JEDEC spec including mode registers, timing parameters, refresh operations, initialization, calibration, training, power management, and error handling.

+ Experience with verification for a full product cycle from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff

+ Experience creating, maintaining, or integrating test benches, checkers and stimulus using Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), and optionally Python based post-processing checking

+ Aptitude for writing scripts/software with industry standard languages like Python

+ Experience applying generative AI to day-to-day tasks

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

Microsoft will accept applications for the role until June 23rd, 2025.

\#MicrosoftSiliconISDV #SCHIE #AHSI

Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .