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Summary:

Meta is looking for an experienced ASIC Packaging Engineer, Signal Integrity, and Power Integrity focus for its ASIC packaging team to support the development of custom Silicon for Infrastructure as well as to develop packaging solutions that are optimal for our ASIC roadmap. We are building a competency in Packaging technology to support the development of custom silicon and looking for expertise in hardware development and integration of machine learning clusters, both server and fabric with focus on the impact they can create as part of a world-class engineering team.

Required Skills:

Package Design Engineer Responsibilities:

1. Drive chip-package-system co-design by driving signal and power integrity requirements analysis and optimization to involved in the product definition and optimize chip floorplan, power tree structure, netlists, etc for High Performance Computing based on 2.5D/3D package technology

2. Hands on experience in interposer or fanout package design for both organic and inorganic interposer with or without bridges such as Cowos-L, cowos-R, EMIB, embedded fanout bridge from OSAT

3. Hands on experience of substrate design and trade off relative to SI/PI, mechanical, thermal and electrical analysis

4. Involvement and how they use package design to improve the chip, what kind of hands on experience (Derek for preS). They will be working on MTIA. (less so pcb design, this is a good to have. Not a must). Focus on (a)What kind of design tools they have used

5. Drive package level Lead ASIC package SI/PI design activities, including substrate stackup/material selection, design guide implementation, layout review, and post-layout analysis

6. Lead pre-layout and post-layout simulation flow with a focus on high-speed interface and PDN, create simulation models and develop simulation methodology for SIPI design

7. Lead SIPI validation methodology and develop detailed engineering test plans

8. Conduct post Si validation and qualification of high speed interface for ASICs

9. Validate high speed interface and PDN impedance in lab to correlate simulation results and improve design flow

10. Work closely with Architecture, ASIC, Mixed Signal, Package, and PCB Design teams to design and ensure package/system SI/PI performance meets expectation before Gerber out, also work closely with Design Validation teams to support SI/PI failure analysis

11. Package/Board power delivery network AC+DC simulation for low-voltage/high-current supplies

12. Development of next generation memory interface considering Input/Output Physical Layer (IO PHY), SI/PI and physical design

Minimum Qualifications:

Minimum Qualifications:

13. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

14. Perform package design for advanced custom silicon comprising single-chip/multi-chip and 3D or wafer packaging. This includes: design feasibility studies and analyses, package design/layouts based on silicon chip IO, electrical performance and system ID/form factor requirements

15. Participate in silicon architecture/package/PCB/system co-design work collaborating with downstream system design teams and upstream silicon designers to develop holistically optimal solutions

16. Co-work with internal silicon, architecture and system teams and externally engaged partners, ASIC design partners, foundry and OSAT and substrate vendors

17. Perform design analysis and what-if scenarios for novel packaging schemes such as 2.5D/3D and heterogeneous integration to improve bandwidth, power efficiency and package form factor for next generation versions of current products

18. Lead package development to establish package manufacturability and reliability

19. Collaborate with multi-functional teams with in Meta and define package requirements

Preferred Qualifications:

Preferred Qualifications:

20. Perform package design for advanced custom silicon comprising single-chip/multi-chip and 3D or wafer packaging. This includes: design feasibility studies and analyses, package design/layouts based on silicon chip IO, electrical performance and system ID/form factor requirements

21. Participate in silicon architecture/package/PCB/system co-design work collaborating with downstream system design teams and upstream silicon designers to develop holistically optimal solutions

22. Co-work with internal silicon, architecture and system teams and externally engaged partners, ASIC design partners, foundry and OSAT and substrate vendors

23. Perform design analysis and what-if scenarios for novel packaging schemes such as 2.5D/3D and heterogeneous integration to improve bandwidth, power efficiency and package form factor for next generation versions of current products

24. Lead package development to establish package manufacturability and reliability

25. Collaborate with multi-functional teams with in Meta and define package requirements

Public Compensation:

$173,000/year to $249,000/year + bonus + equity + benefits

**Industry:** Internet

Equal Opportunity:

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [email protected].