"Alerted.org

Minimum qualifications:

+ Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

+ 2 years of experience with System Level Test (SLT) or product engineering.

+ Experience with ASIC or SoC prototype bring-up, debug, functional verification or functional manufacturing test.

+ Experience with Linux/Unix and Python programming.

Preferred qualifications:

+ Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

+ 10 years of experience in test engineering, product engineering or silicon quality/reliability.

+ Experience with SLT test flow development, test automation, and test deployment actively contributing to technical design and problem-solving.

+ Experience implementing secure manufacturing solutions including provisioning, Efuse and programming, life-cycle management, and SoC security.

+ Familiarity with SLT test handlers from Advantest, Teradyne, Chroma, or others.

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role you will help build the SoC’s that power these data centers by developing and deploying comprehensive test solutions with Automatic Test Equipment (ATE) for New Product Introduction (NPI) and hand-off for High Volume Manufacturing (HVM) at wafer fabs and OSATs. This is an opportunity to create silicon and follow it into the field to close the loop back to design and test for the next generations of chips. You will be a key member of the team that drives SLT manufacturing test development and deployment. You will support hardware development, test integration, test automation, and test deployment. You will work closely with cross functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. A strong understanding of Integrated Circuits (IC) flows, wafer processing, testing, qualification and failure analysis is expected. You will work with various groups to develop tests, automation methodologies, test program release, etc. You will also work on releasing cost effective production test solutions into mass production.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

+ Develop System Level Test (SLT) solutions for custom Application-Specific Integrated Circuits (ASIC) and SoC’s by specifying hardware and integration requirements, driving vendor interactions, developing software frameworks and test modules, and integrating test cases from silicon validation and system software and test teams.

+ Partner with data center server and accelerator design teams to realize practical test solutions leveraging system design and test elements.

+ Partner with hardware and software teams to evaluate functional device yield and performance across various operating conditions, characterize hardware/software interaction, and develop effective production screens to reduce defective parts per million.

+ Integrate test software and hardware solutions with robotic chip handlers, drive bring-up of the fully integrated solution in internal and partner NPI labs, transfer all collaterals needed for HVM at Offshore Assembly and Test (OSAT) facilities, and provide ongoing HVM support.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCP_EEO_Post.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.