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Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

The Data Processing Unit (DPU) team brings together state-of-the-art software and hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data streams. Thanks to its integrated design, this solution empowers teams to operate with increased agility and deliver significantly superior performance compared to CPU-based alternatives

Microsoft DPU team in Santa Clara is looking for a Senior Design For Test Engineer to help develop their next generation complex SoCs and to join our team. It’s a great opportunity to gain exposure all the way from DFT architecture to post silicon bring up.

The candidate will design, implement, and validate scan, BIST, boundary scan and IJTAG features in our SoCs. Candidate will work closely with cross functional teams to generate and validate production vectors and work on silicon bring up.

Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

Responsibilities

+ Boundary scan insertion and validation

+ MBIST insertion and validation including shared bus MBIST architecture

+ EDT, SSN, and logic bist insertion and validation

+ ATPG pattern generation and validation for various fault models

+ Timing constraint development for DFT structures

+ Design and integrate test structures such as fuse, repair and on chip clocking controllers

+ Embody our culture (https://careers.microsoft.com/v2/global/en/culture) and values. (https://www.microsoft.com/en-us/about/corporate-values)

Qualifications

Required qualifications:

+ Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience

+ OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience

+ OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience

+ OR equivalent experience.

+ 2+ years of industry experience as a Design For Test (DFT) engineer.

+ Hands on experience with Tessent tools for scan and Memory Built In Self Test (MBIST).

+ Hands on experience simulating and debugging Register Transfer Language (RTL) and gate level Design For Test (DFT) features.

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings:

+ Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

Preferred qualifications:

+ Bachelor’s degree in engineering with 5 years of experience as a DFT engineer or a Master’s degree in engineering with 3 years of experience as a DFT engineer.

+ Experience in designing and implementing In System Test structures

+ Experience with Synopsys tools for synthesis and STA

+ Experience with System Verilog for design and verification

+ Post silicon bring up and production vector generation is a plus.

+ Knowledge of Perl, Tcl or Python scripting languages

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: US corporate pay information | Microsoft Careers (https://careers.microsoft.com/v2/global/en/us-corporate-pay.html)

Microsoft will accept applications for the role until July 26th, 2025.

\#DPU

\#SCHIE

\#azurehwjobs

Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .