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NVIDIA Networking Clock design team is looking for experienced top notch ASIC design engineer to work on next generation of NVIDIA Networking chips. We're looking for profound and multi-disciplinary background in Clock design domains to lead Clocks Micro-Architecture activities. This role requires working with multiple teams as Architecture, IP, Physical design, Timing and Post-Si teams. Complexity of clocking scheme has grown substantially over recent chip generations with increased focus on performance, power and quality. Modern Clocking design needs to balance high frequency clocks with power, DFx, noise, circuit and physical design constraints.

What you will be doing:

+ Working on next generation of Networking Switch, NIC and SoC products.

+ Micro architect and design next generation clock topologies and modules.

+ ASIC Clock scheme definition.

+ Improve Power, Performance, and Area (PPA) of state-of-the-art NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.

+ Collaborate with Physical design and timing team to evaluate Clocking concerns and come up with solutions for supporting high speed Clocking.

+ Understand physical aspects of the chip and develop enhanced clock distribution techniques.

+ Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.

+ Support Post-Si debug, characterization and productization activities.

What we need to see:

+ BSc or MSc degrees in EE or equivalent experience.

+ At least 6+ years of work experience in RTL design, Gate-Level and Circuit design optimization.

+ Deep understanding of logic optimization techniques and PPA trade-offs.

+ Excellent interpersonal skills and ability to collaborate with multiple teams.

+ Excellent problem solving and debugging skills.

Ways to stand out from the crowd:

+ Prior experience in RTL design (Verilog), verification and synthesis.

+ Clock IPs profound knowledge: PLL, DLL, Compensator.

+ Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a bonus. Prior experience in implementing on-chip clocking networks.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

You will also be eligible for equity and benefits (https://www.nvidia.com/en-us/benefits/) .

Applications for this job will be accepted at least until July 29, 2025.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.