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Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the **Microsoft’s Compute Silicon & Manufacturing Engineering team** is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a **Principal Physical Design Engineer** with **CPU Core expertise** to join the team.

\#SCHIE #CSME \#Siliconjobs #CCDO

Responsibilities

+ Responsible for Core CPU partition (L1-L2) or similar ownership with PPAS (Power, Performance, Area & Schedule) target accomplishments.

+ Responsible for RTL to GDS implementation in Physical Design domain.

+ Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners as essential.

+ Lead & influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach.

+ Lead and manage floor-planning and design planning activities to optimize timing-critical and large sub-chips for power, performance, and area (PPA).

+ Drive end-to-end execution from synthesis through place-and-route for Core CPU, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.

+ Develop and implement robust clock distribution strategies that meet design specifications.

+ Make sound technical trade-offs between power, area, and timing to achieve optimal design outcomes.

+ Foster collaboration across teams to deliver the best possible solutions, aligned with a One Microsoft mindset.

+ Demonstrate technical expertise across various domains of Physical Design & Timing Signoff.

+ Clear communications on project status & planning.

+ Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.

Qualifications

Required Qualifications:

+ Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience

+ OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience

+ OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience

+ OR equivalent experience.

+ 8+ years of experience in semiconductor design.

+ 8+ years experience with Physical Design domain implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.

Other Requirements:

+ Ability to meet Microsoft, customer and/or government security screening requirements arerequired for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

+ Experience in CPU Core , and/or Timing Critical IP design with multiple production tape-outs using advanced foundry process nodes.

+ Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.

+ Own complete PD execution of Critical blocks/Partitions/Sub-systems/Sub-chips instantiating/integrating multiple other Physical partitions. Be fully hands-on in your individual ownerships as individual contributor and collaborate cross-team as required.

+ Proficient in timing & power rollup methodologies with hands-on experience.

+ Deep expertise in timing constraints (functional & DFT), static timing analysis (STA), and timing-power optimization.

+ Communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.

+ Understanding of CPU design trade-offs across power, performance, and area (PPA).

+ Hands-on experience with CPU specific clock tree synthesis (CTS) and global clock distribution in complex multi-voltage, multi-clock, multi-domain, and low-power designs.

+ Experienced in industry-standard EDA tools (Synopsys or Cadence).

+ Proficiency in Engineering Change Order (ECO) implementation for power and timing convergence, with solid knowledge of functional and DFT ECO closure methodologies.

+ Track record in mentoring, influencing teams, and driving alignment through clear and effective communication.

+ Understanding of formal equivalence checks, low power (LP), Unified Power Format (UPF), reliability, signal integrity (SI), and noise analysis.

+ Analytical and problem-solving skills, complemented by advanced scripting capabilities in Perl, TCL, and Python.

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $139,900 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: US corporate pay information | Microsoft Careers (https://careers.microsoft.com/v2/global/en/us-corporate-pay.html)

Microsoft will accept applications for the role until Oct 9th, 2025.

\#SCHIE #Siliconjobs #CSME #CCDO

Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations (https://careers.microsoft.com/v2/global/en/accessibility.html) .