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ASIC Engineering Technical Leader

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+ Location:San Jose, California, US

+ Area of InterestEngineer - Hardware

+ Compensation Range191400 USD - 281400 USD

+ Job TypeProfessional

+ Technology InterestNetworking

+ Job Id1451408

The application window is expected to close on: Nov 20, 2025.

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Meet the Team

You will be part of the Silicon One development organization as an ASIC implementation engineer in San Jose, CA. As a member of this team you will be involved in crafting cutting edge next generation networking chips.

Your Impact

You will be the lead to drive the DFT/DFx and quality process through the early product life cycle: the architecture definitions, RTL implementation and quality checks. You will also be engaged in relevant development of flow/methodologies, test plans, tape-out sign-off requirements, post silicon validation, production yield & DPPM support.

Key Responsibilities:

+ Responsible for development of the comprehensive Design-for-Test (DFT) & DFx solutions and architectures that support ATE screening, in-system test, debug and diagnostics needs of the design.

+ Lead the RTL implementation from the architecture specifications and required RTL quality checks implementations.

+ Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug methodologies and standards.

+ Work with the team on DFT challenge identification, cross-functional solution brainstorming and implementation plan development, and lead a team of engineers to deliver expected implementations on schedule.

**Minimum Qualifications** :

+ 10+ years of experience on ASIC hardware development

+ Prior experience on hardware design specifications and verification plan/matrix, RTL & testbench implementations.

+ Prior experience on Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.

+ Post-silicon test bring up and debug experience; Ability to analyze and root cause test failures on silicon.

+ Prior experience on RTL QA checks, including lint & CDC

Preferred Qualifications

+ Scripting skills: Tcl, Python/Perl.

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