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ASIC Manager, Design Verification
- Meta (Sunnyvale, CA)
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Summary:
Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. To apply, click “Apply to Job” online on this web page.
Required Skills:
ASIC Manager, Design Verification Responsibilities:
1. Build successful world-class complex SoC and IP for data center applications, and end-to-end SoC/ASIC development.
2. Responsible for firmware and driver development, and front-end and back-end standard cell ASIC development (including algorithm and architectural modeling, silicon architecture, micro-architecture, RTL development).
3. Design Verification, FPGA emulation, co-simulation, simulation acceleration, synthesis, and post-silicon validation.
4. Perform cross-functional collaboration and partner with internal and external cross-functional teams, across all levels of a corporation, from executives, team managers and individual contributors including development engineers, capacity planners and supply chain experts.
5. Define, debug, implement and deliver system solutions around purpose built ASICs, and create soft and hard IP identification, selection and IP licensing.
6. Provide technical mentorship, plan work assignments, and manage performance reviews for design verification engineers on the team.
7. Domestic and International Travel Required 10%.
Minimum Qualifications:
Minimum Qualifications:
8. Bachelor's degree (or foreign equivalent) in Computer Engineering, Computer Science, Electrical Engineering or related field and 5 years of progressive, post-baccalaureate work experience in the job offered or in a computer-related occupation
9. Experience must include 5 years in the following:
10. One or more HDL languages (System Verilog, Verilog), and one or more scripting languages (TCL, Python, Perl, or Shell-scripting)
11. Standard Cell ASIC development from Architecture through to GDSII release (including pre-silicon emulation and co-simulation) and post-silicon
12. One or more Verification languages (UVM, System Verilog) creating test plans and defining coverage
13. C/C++/SystemC
14. Functional verification based on Simulation-Acceleration
15. EDA tools like VCS, NCSIM, or Verdi
Public Compensation:
$304,779/year to $336,600/year + bonus + equity + benefits
**Industry:** Internet
Equal Opportunity:
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [email protected].
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