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We are now looking for a Senior ASIC Design Engineer - DFX

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips.

What You’ll Be Doing:

+ As a key member of our DFX Methodology Team, you will play a critical role in shaping the architecture, design, implementation, and verification of DFT IPs for our next-generation SoC products. You’ll help drive innovation across the full silicon lifecycle—from pre-silicon to post-silicon—while mentoring and collaborating with cross-functional teams.

+ Own the architecture, design, and verification of DFT IPs for cutting-edge SoC designs.

+ Develop, deploy, and enhance DFT methodologies for scalability and future product needs.

+ Define and align feature sets by working closely with architects, platform, and software teams.

+ Partner with design, verification, synthesis, timing, and backend teams to ensure cohesive integration.

+ Create and execute test plans to support both functional and DFT full-chip verification.

+ Support post-silicon bring-up and validation efforts including debug and issue resolution.

+ Mentor junior engineers on test design strategies and trade-offs related to cost, quality, and performance.

What We need to see:

+ Master’s degree (or equivalent experience) in Electrical Engineering or related field.

+ 5+ years of hands-on experience in SoC architecture, RTL design, and verification.

+ Strong proficiency in micro-architecture and RTL development using Verilog.

+ Experience with formal verification using JasperGold is a plus.

+ Deep expertise in DFT design, methodology, and implementation.

+ Familiarity with related domains such as clocking, STA, place & route, and power optimization.

+ Experience in post-silicon bring-up on ATE, including understanding of pattern formats, test program development, and failure analysis.

+ Proficiency in scripting languages such as Python, Perl, or Tcl.

+ Excellent communication skills and a collaborative mindset—with a curiosity and passion for solving complex technical challenges.

This is your chance to join a high-impact team driving the foundation of next-generation semiconductor innovation. If you’re passionate about DFT and SoC architecture, and want to work in a fast-paced, collaborative environment where your ideas make a difference—we’d love to hear from you.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

You will also be eligible for equity and benefits (https://www.nvidia.com/en-us/benefits/) .

Applications for this job will be accepted at least until October 28, 2025.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.