• ASIC Engineer, Power

    Meta (Sunnyvale, CA)


    Summary:

    Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. To apply, click “Apply to Job” online on this web page.

    Required Skills:

    ASIC Engineer, Power Responsibilities:

    1. Develop power vectors for estimation and optimization.

    2. Low-power design of ASIC modules.

    3. Run industry standard EDA power simulation tools on customized ASIC designs.

    4. Power estimation and optimization strategies for all layers of abstraction in silicon design, from architecture to physical design.

    5. Develop power vectors for estimation and optimization.

    6. Low-power design of ASIC modules.

    7. Run industry standard EDA power simulation tools on customized ASIC designs.

    8. Power estimation and optimization strategies for all layers of abstraction in silicon design, from architecture to physical design.

    9. Develop internal tooling for performance and power improvement for ASICs.

    10. Reduce arithmetic unit and data-path power while reducing area and increasing performance in new generation hardware accelerators.

    11. Formulate circuit and data-path abstractions using mathematical models.

    Minimum Qualifications:

    Minimum Qualifications:

    12. Bachelor's degree (or foreign degree equivalent) in Computer Science, Engineering, Mathematics, Physics, Applied Sciences, or a related field and 2 years of experience in the job offered or in a computer-related occupation

    13. Experience must include 2 years of experience in the following:

    14. C, C++, Java, TCL, and Python Programming

    15. Writing RTL code using Verilog/SystemVerilog or VHDL

    16. Mathematical modeling of ASIC physical feature phenomenon

    17. Frontend power analysis and optimization tools (Prime Power RTL / RTL Architect) with experience in RTL design or validation

    18. Backend power estimation tools and flows including development and analysis (Prime Power / Power Replay) to perform power estimation, analysis and optimization at various stages of the design

    19. UPF generation, verification (VC Low Power), and signoff for complex SoC projects

    20. Understanding of Computer Architecture including various design tradeoffs and how they affect power and

    21. Experience generating Thermal and Power maps to understand hotspots and power density in an ASIC using mathematical modeling software (MATLAB)

    Public Compensation:

    $187,029/year to $192,170/year + bonus + equity + benefits

    **Industry:** Internet

    Equal Opportunity:

    Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

     

    Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [email protected].