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We are seeking a talented **Chip Architect** to join our ACS team which develops cutting edge ASSP ICs. This individual will play a key role in **architecting mixed-signal chips** , **partitioning digital and analog design blocks** to optimize functionality and performance, especially for **high-speed clock and data paths** , and to **drive best-practices in Design for Verification and Design for Test.**

This individual will:

+ Work with our customers, systems, analog/digital design, layout, verification, and test/validation teams to define the chip architecture to meet all project requirements.

+ Own the chip top-level integration. Drive the integration process from architectural definition through PG, ensuring robust functionality, parametric compliance, and on-time first-pass success.

+ Partition functionality between analog and digital domains according to best-practices, to be rigorously verifiable (Design for Verification), and to be testable (Design for Test).

+ Architect high-speed clock and data paths across analog and digital domains to meet chip performance objectives and to allow for robust sign-off. Define the methodology for sign-off of clock and data paths across analog and digital domains (e.g. CDC, RDC, formal, extractions, STA, margining, jitter, cross-talk, EMIR, aging, GLS, DMS, AMS, Spectre and Xcelium simulations, etc.).

+ Enable rigorous DMS and AMS verification through design partitions that are friendly to modeling, and by driving a rigorous block modeling methodology. Create and maintain models and/or drive model creation with stakeholders. Create and maintain flows to manage netlisting and config hierarchy selection for AMS and DMS flows (e.g. schematic netlist, real-number model, simple logical model, Verilog-AMS electrical or wreal model, RTL, Gates/SDF, etc.).

+ Define block handoff requirements and acceptance checks for analog IP and digital IP. Drive sign-off checks. Increase the use of automation to ensure consistency in results and to reduce manual effort.

+ Effectively work with project management and cross-functional team members to ensure all project deliverables meet requirements and schedules, and to ensure smooth integration according to plan.

Why TI?

+ Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.

+ We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI (https://edbz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/pages/4012)

+ Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us.

About Texas Instruments

Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com .

Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, creed, disability, genetic information, national origin, gender, gender identity and expression, age, sexual orientation, marital status, veteran status, or any other characteristic protected by federal, state, or local laws.

If you are interested in this position, please apply to this requisition.

Minimum requirements:

+ 10+ years of experience as a digital designer, including 5+ years as a design lead.

+ A thorough understanding of digital logic design, timing, and the Verilog and SystemVerilog languages.

+ Experience in design and verification of high-speed clock and data paths, including sign-off checks such as CDC, RDC, STA, and GLS.

+ Solid understanding of analog design, and the capability to explain operation at schematic-level.

+ Strong understanding of mixed-signal and digital verification flows (AMS / DMS / TLDV / DDV), and modeling of analog blocks.

+ Strong leadership, communication, cross-team collaboration skills, and customer-facing skills.

+ Strong analytical and problem-solving skills.

+ Ability to work in a fast-paced and rapidly-changing environment.

Preferred qualifications:

+ Experience as a chip architect or integration lead, or experience of closely working with individuals in these roles.

+ Experience in design or verification of PLLs, DLLs, and clock/data recovery (CDR) circuits.

+ Direct experience as a systems engineer, or experience of closely working with a systems engineer or a systems architect.

+ Experience in modeling analog blocks such as real-number modeling (SystemVerilog EEnet or Verilog-AMS wreal), logical modeling (Verilog, SystemVerilog), or electrical modeling (Verilog-AMS).

+ Experience with top-level timing closure across digital and analog boundaries.

+ Experience with creating and maintaining chip schematics/symbols in Cadence Virtuoso.

**ECL/GTC Required:** Yes