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Overview

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Principal Design for Debug Execution Lead to help achieve that mission.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the SCHIE team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a Principal Design for Debug Execution Lead for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a **Principal Design for Debug Execution Lead** to join the team.

Responsibilities

In this role on the team, your responsibilities will include:

+ Define the micro-architectural implementation spec for debug IP’s, fabrics & implement the micro-architectural specification in Verilog or System Verilog.

+ Lead a team of engineers for IP & product DFD deliverables and support individual contributors in their own career growth.

+ Work as part of DFX (Test & Debug) team & closely collaborate with highly energetic cross functional team members (system architects, front-end & back-end design verification, and post-si validation folks) with respect and with One Microsoft mentality to establish synergies.

+ Refine Debug execution methodology and use of industry/home-grown tools to ensure design quality, effectiveness & speed up execution.

+ Hold a primary role in enabling silicon by working directly with validation & fleet engineers to bring up debug capabilities and to help with diagnostics & screening.

+ Work closely on Debug tool POC & roadmap associated with the RTL features implemented in design.

+ Assess and then refine the implementation for debug coverage, area, power and performance. Ensure quality with checks covering Lint, CDC, Low Power intent and more.

+ Delight your customers by delivering cutting-edge debug IP’s & infrastructure for custom SoC designs that can perform complex and high-performance functions.

Qualifications

Required Qualifications:

+ Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.

Other Requirements:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

+ Efficient in designing debug IP’s & SOC integration. Includes building and integrating any of the Debug IPs such as the ones provided by ARM Coresight.

+ Proficiency in System Verilog & scripting along with excellent knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting).

+ Good understanding in clock crossing techniques & UPF (Low power intent).

+ Previous experience working on post-silicon debug / validation, especially during power ON & FA/FI.

+ Hands on contribution towards Debug Architecture along with good knowledge of Industry standard standards.

+ Proactive & self-motivated, eager to learn and contribute in a team environment, committed and accountable. Confident problem solver who thrives under pressure to find new, creative solutions.

\#SCHIE

Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $139,900 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

https://careers.microsoft.com/us/en/us-corporate-pay

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations. (https://careers.microsoft.com/v2/global/en/accessibility.html)