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Overview

Microsoft's mission is to empower every person and every organization on the planet to achieve more. At Microsoft Quantum, we aim to empower science and scientists to solve the world's biggest problems by realizing advanced computing platforms at the intersection of high-performance computing, artificial intelligence (AI), and quantum information technology. For more information about our team, visit https://www.microsoft.com/en-us/quantum .

We are seeking an exceptional **Principal Quantum Engineer – Application-specific Integrated Circuit (ASIC) Design Lead** to architect, design, and deliver next‑generation digital control and mixed‑signal systems spanning cryo‑complementary metal-oxide semiconductor (CMOS), room‑temperature instrumentation, and Field-programmable gate array (FPGA)‑to‑ASIC hardened pipelines. This position offers an opportunity to have a meaningful influence on a revolutionary technology. The role involves deep, technical work in a small, collaborative environment. We are looking for someone who is as passionate about their own contribution as they are to empowering and inspiring others. The role sits at the intersection of device physics, quantum‑scale electronics, and scalable semiconductor engineering. The ASIC Design Lead will guide the full lifecycle—from concept architecture to tape‑out—while shaping design flows and process-design kits (PDKs) that enable deep collaboration with foundry partners.

Responsibilities

+ Cryo‑CMOS Control Chip Architecture & Design: Lead the design of ultra‑low‑temperature CMOS control ASICs for cryogenic quantum systems.

+ Collaborate with device, packaging, and quantum hardware teams to co‑optimize performance, noise, thermal load, and reliability.

+ Own the architecture and implementation of room‑temperature instrumentation logic, including data‑acquisition pipelines, control sequencing, and high‑speed digital interfaces.

+ Lead the migration of FPGA‑based prototypes into production‑grade ASIC implementations, including register-transfer level (RTL) refinement, timing closure, and power/performance optimization.

+ Establish robust verification, emulation, and bring‑up workflows to ensure seamless transition from FPGA to custom silicon.

+ Develop and maintain layout methodologies and physical‑design flows that support advanced cryo‑CMOS and mixed‑signal ASICs.

+ Work closely with foundry partners to influence and refine PDK features, device models, and design‑rule evolution.

Other:

+ Embody our Culture (https://careers.microsoft.com/v2/global/en/culture) and Values (https://www.microsoft.com/en-us/about)

Qualifications

Required/Minimum Qualifications:

+ Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years experience in industry or in a research and development environment OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 10+ years experience in industry or in a research and development environment OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years experience in industry or in a research and development environment

+ OR equivalent experience.

Other Requirements:

+ Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings:

+ Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

+ Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

+ Ability to work in an “AI-first” environment using modern AI tools to accelerate discovery through both hardware and software development.

+ Ability to design and build AI agents/copilots that assist with experiment setup, log triage, measurement report generation, protocol templating, and knowledge retrieval (e.g. instrument manuals, design docs).

Additional/Preferred Qualifications:

+ Build scalable workflows that enable multi‑institutional collaboration, including versioned design environments, shared Intellectual Property (IP) libraries, and reproducible layout pipelines.

+ Mentor internal and external teams on design‑flow best practices, physical‑design constraints, and cross‑domain integration.

+ 7+ years of related technical engineering experience.

+ 10+ years of industry experience in logic design delivering complex solutions.

+ Successful  ASIC tape outs in deep sub-micron technologies.

+ Good background in debugging designs as well as simulation environment.

+ Knowledge of verification principles, testbenches, Universal Verification Methodology (UVM), and coverage.

+ Deep experience with electronic design automation (EDA) software for digital design (Cadence suite).

+ Experience/exposure to low-temperature circuit design and measurements is desirable.

+ Knowledge of quantum physics, behavior of semiconductors at cryogenic temperatures is desirable.

+ Excellent team player and excellent communication skills.

+ Ability to be flexible and adapt to new situations in a rapidly changing research environment.

+ Demonstrated experience with report writing and documentation.

\#Quantum #QuantumCareers #MDQCareers

Quantum Engineering M6 - The typical base pay range for this role across the U.S. is USD $163,000 - $296,400 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $220,800 - $331,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:

https://careers.microsoft.com/us/en/us-corporate-pay

This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations. (https://careers.microsoft.com/v2/global/en/accessibility.html)