- Microsoft Corporation (Mountain View, CA)
- … tools such as Synopsys, and Cadence tool suites. + Partner effectively with PD, DFT , STA flow, CAD teams, and EDA tool vendors to ensure seamless integration ... the Cloud infrastructure. We are looking for a **Senior Physical Design Engineer ** to join the team. **Responsibilities** + Accountable for Design-for-Test ( DFT… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …who want to make an impact on the world of technology. Job Title: Lead Application Engineer Location: Tampere, Finland Reports to: AE Director Job Overview: This ... variety of digital implementation and support activities associated with Cadence EDA tools for Synthesis, Logical Equivalency Checking (LEC), Design-for-Test ( DFT… more
- SanDisk (Milpitas, CA)
- …forward. **Job Description** We are looking for an experienced **Digital Physical Design Engineer ** to work whole digital SPR flow from RTL to GDS, include ... Synthesis, DFT scan insertion, PNR, STA timing analysis, IRdrop power...**Programming & Scripting:** Proficiency in TCL/TK, Perl scripting. + ** EDA Tools:** Familiarity with Cadence, Synopsys digital flow include… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …skills Preferred + Prior experience with IC digital implementation flows and font-end EDA tools including Synthesis, DFT , and Logical Equivalence Checking + ... an impact on the world of technology. Sr Principal Application Engineering (AE) - a blend of pre-sales, post-sales...Prior experience with IC digital implementation flows and backend EDA tools including Place and Route, IR Drop, backend… more
- SanDisk (Milpitas, CA)
- …where you'll be at the center of innovation. We are looking for an experienced Engineer to lead and deliver projects for our Memory Design team. This is a great ... RTL linting, clock domain crossing (CDC) analysis, design integration, synthesis, DFT , timing analysis and closure + Balance design trade-offs with modularity,… more
- Amazon (Cupertino, CA)
- …of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring ... Drive Optimizations in CAD flows/methodologies for PPA and TAT improvements Work with EDA tool vendors to evaluate new methods, resolve bugs, improve usability. Fine… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
- Amazon (Cupertino, CA)
- …AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our ... performance at low cost. You'll provide leadership in the application of new technologies to large scale deployments in...- Interface directly with RTL, Physical Design, Package Design, DFT and other teams to improve methodologies and efficiencies… more
- Amazon (Cupertino, CA)
- …hours/week) for 12 consecutive weeks during summer. By applying to this position, your application will be considered for all locations we hire for in the United ... to improve physical design flows and methods * Collaborate with RTL, DFT designers to ensure high quality design implementation Basic Qualifications Bachelors'… more
- Amazon (Sunnyvale, CA)
- …the latest generation of Echo devices is looking for a Senior SoC Design - EM/IR Engineer to continue to innovate on behalf of our customers. We are a part of Amazon ... workflows to improve PDN analysis efficiency. * Partner with EDA tool vendors to enhance and customize EM/IR analysis...right vectors for different types of analysis including functional, DFT and other scenarios for which power numbers are… more