• Leader, Engineering - Silicon One Customer…

    Cisco (San Jose, CA)
    …at any time. **Meet the Team** Cisco Silicon One is the center of Cisco's ASIC design and is driving the development of next-generation network devices for the AI/ML ... SDK functionalities, including working closely with the rest of our Core ASIC Group (CAG). Additionally, you'll collaborate with leaders across different functions… more
    Cisco (01/08/26)
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  • Sr. Full Chip Physical Design Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    …cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing ... level design for testability (DFT) planning + Collaborate with chip architects, ASIC engineers, package engineers and block level physical design engineers to drive,… more
    SpaceX (01/07/26)
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  • Sr. SerDes Characterization and Validation…

    SpaceX (Irvine, CA)
    …cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing ... environmental conditions specific to space applications + Work closely with the ASIC design team to add/improve testability and define various loopback and test… more
    SpaceX (01/07/26)
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  • Design Verification Engineer

    Arrow Electronics (Mountain View, CA)
    …Principal Accountabilities * Responsible for architecting Verification Environment for ASIC SoC and providing verification support from defining verification plan ... SoC test FW and create test plan documentation to cover ASIC features. * Develop and debug SoC ASIC platform test FW and specific tests in C/C++. * Partner… more
    Arrow Electronics (12/25/25)
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  • Hardware Engineer

    Meta (Menlo Park, CA)
    …suppliers, to define product roadmap and program 2. Specify, design, and develop CPU/GPU/ ASIC based compute hardware solutions, and ASIC enabling hardware 3. ... **Preferred Qualifications:** Preferred Qualifications: 10. 6+ years of experience with designing ASIC verification & bring up hardware 11. 6+ years of experience… more
    Meta (12/20/25)
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  • Senior Power Architecture and Optimization…

    NVIDIA (Santa Clara, CA)
    …team is responsible for analyzing fullchip and unit-level power data, and driving ASIC teams to improve their units' power efficiency; and is responsible for ... this team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement… more
    NVIDIA (12/16/25)
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  • Nvidia 2026 Internships: PhD Hardware Research…

    NVIDIA (Santa Clara, CA)
    …+ Design and implement novel approaches to circuit and VLSI design, including ASIC development and advanced EDA methodologies. + Collaborate with other team members, ... Security + High-Speed Logical Design + Novel Digital VLSI Circuits ASIC and VLSI + ASIC and VLSI Design Techniques + ML Accelerators + Hardware/software… more
    NVIDIA (12/01/25)
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  • R&D Engineer Physical Design

    Broadcom (San Jose, CA)
    …nearly every major segment of the semiconductor industry-including AI-to build advanced ASIC solutions. Join the Design Implementation team within Broadcom's ASIC ... to product release, becoming a key contributor to all aspects of physical ASIC design. **Job Duties and Responsibilities may include:** + Communicating directly with… more
    Broadcom (11/26/25)
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  • Sr Engineer HW/SW (System Architecture)

    Palo Alto Networks (Santa Clara, CA)
    …Processor Tool Chain Development - Assembler, Debugger, Simulator + Infrastructure to support ASIC team development and verification + ASIC microcode and device ... In-depth knowledge of networking equipment & architectures - system hardware, CPUs, ASIC etc. + Experienced in networking protocols - mobile, routing, transport… more
    Palo Alto Networks (11/21/25)
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  • Senior Timing Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …experience) in Electrical or Computer Engineering with 3 years' experience in ASIC Design and Timing. + Good understanding of modeling circuits for sign-off ... standard cells/memory/IO IP modeling and its usage in the ASIC flow. Hands-on experience in advanced CMOS technologies, design...Python. C++ is a plus. Familiarity with industry standard ASIC tools: PT, ICC, Redhawk, Tempus etc. + Strong… more
    NVIDIA (11/20/25)
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