• Software Engineering Technical Leader - Silicon…

    Cisco (San Jose, CA)
    …also with architecture and design teams to define the next generation of ASIC products being developed. **Your Impact** As part of Silicon One Customer Engineering ... with architecture and hardware teams to shape the next generation of ASIC products. You are an accomplished technical leader with extensive experience in… more
    Cisco (01/08/26)
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  • Head of Program Management

    Insight Global (Santa Clara, CA)
    …a semiconductor client in Santa Clara, CA. This person will lead ASIC and platform development from architecture to production, coordinate cross-functional teams and ... of experience in semiconductor program management, with a strong background in ASIC development. *Proven ability to lead and drive large-scale, complex semiconductor… more
    Insight Global (01/07/26)
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  • Sr Thermal Engineer (Hardware)

    Palo Alto Networks (Santa Clara, CA)
    …PAN product development thermal effort in both NPI & Sustaining + Support ASIC team in the determining thermal package performance prior to release for manufacture ... operations, manufacturing, and quality teams + Excellent understanding of ASIC package design Communication + Excellent cross-functional communication skills, with… more
    Palo Alto Networks (01/07/26)
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  • Senior Manager - Business Operations, Amazon Leo

    Amazon (Sunnyvale, CA)
    …a refugee or granted asylum. Key job responsibilities Be the Leader for ASIC Global Business Operations. Develops operations models and oversees supply chain, sales ... sales orders, and fulfillment. - Lead cross-functional Initiatives to establish wafer and ASIC supply chain process and overall structure of the business. - Leading… more
    Amazon (01/07/26)
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  • Software Engineer I

    Cadence Design Systems, Inc. (San Jose, CA)
    …function to bridge and gate-keep the full integration, validation, and characterization of ASIC , HW/PCB, SW, FW, and FPGA subsystems in the whole development cycle. ... design simulation runs. Debug and isolate system-level issues down to ASIC /FPGAs, host servers, subsystems, firmware modules, runtime diagnostics. + Develop silicon… more
    Cadence Design Systems, Inc. (01/07/26)
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  • Non Destructive Test Technician - Tech 2/3 - DOD…

    Northrop Grumman (Palmdale, CA)
    …+ Requires certifications in non-destructive testing in accordance with regulations. B ** asic Qualifications Level 2:** + High School Diploma/GED and 2 years of ... of time, as determined by the company to meet its business needs. B ** asic Qualifications Level 3:** + High School Diploma/GED and 4 years of Non-Destructive Test… more
    Northrop Grumman (01/06/26)
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  • Senior/Principal Electronics Engineer - High…

    Sandia National Laboratories (Livermore, CA)
    …test engineers in the design and qualification of products. + Design of FPGA/ ASIC based digital and analog circuits, and integration with commercial off the shelf ... firmware design. + Experience in VHDL, Verilog, C, C++, and/or custom ASIC design. + Electrical and environmental qualification testing and documentation experience.… more
    Sandia National Laboratories (01/06/26)
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  • Technologist Software Development Engineering…

    Western Digital (Roseville, CA)
    …pipelines for coverage, reliability, and performance KPIs. * Collaborate across FW/HW/ ASIC ; document standards and best practices. * Adhere to IP/data compliance ... dev & lab host config. * Prior storage FW or networking ASIC validation experience. **Additional Information** Western Digital is committed to providing equal… more
    Western Digital (01/06/26)
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  • Non Destructive Test Technician - Tech 2/3

    Northrop Grumman (Palmdale, CA)
    …test techniques + Completes these and other job duties as instructed **B** ** asic Qualifications Level 2:** + High School Diploma or equivalent GED (education will ... of time, as determined by the company to meet its business needs **B** ** asic Qualifications Level 3:** + High School Diploma or equivalent GED (education will be… more
    Northrop Grumman (01/06/26)
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  • RTL Design Engineer (eInfochips)

    Arrow Electronics (Santa Clara, CA)
    …+ Lead silicon bring-up activities, troubleshoot, and debug PCIe related issues. + ASIC Design and Development: + Design, implement, and verify ASIC components ... with a focus on PCIe physical layer requirements. + Utilize Verilog and SystemVerilog for development, ensuring compliance with performance and design standards. + SerDes Technology: + Extensive knowledge of SerDes technology, including understanding its… more
    Arrow Electronics (12/30/25)
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