- Google (Mountain View, CA)
- …for low power SoCs. + Experience with ARM-based SoCs, interconnects and ASIC methodology. **Preferred qualifications:** + Master's degree or PhD in Electrical ... Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. + 5 years of industry experience with IP design for clocking, interconnects, peripherals etc. + Experience with methodologies for low power estimation, timing… more
- Google (Mountain View, CA)
- …with an emphasis on computer architecture. + Experience in low power digital ASIC design including UPF/CPF, multi-voltage domains, power gating and on chip power ... management. + Experience in design and analysis of power management IPs with a solid understanding of clock, reset, and power sequencing interactions. + Experience in post-silicon validation and debug. + Experience with gate-level SPICE simulations and… more
- Google (Mountain View, CA)
- …like Python or Perl. + Experience with ARM-based SoCs, interconnects and ASIC methodology. **Preferred qualifications:** + Master's degree or PhD in Electrical ... Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. + 10 years of industry experience with IP design. + Experience with methodologies for low power estimation, timing closure, synthesis. + Experience with… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... challenge yourself and be a part of something great, join us today! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized… more
- Amazon (Cupertino, CA)
- …scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... ensuring high design quality and making the right trade-offs. Our team is dedicated to supporting new members. We have a broad mix of experience levels and tenures, and we're building an environment that celebrates knowledge-sharing and mentorship. Our senior… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... challenge yourself and be a part of something great, join us today! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized… more
- Amazon (San Diego, CA)
- …validation of FPGAs using test benches, which can be reused for the ASIC implementation . Run formal verification of complex blocks to ensure functional correctness ... . Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM, System C and DPI-C . Develop a highly automated environment to run regressions that can be used to make builds and… more
- Meta (Sacramento, CA)
- …click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer, Design Verification Responsibilities: 1. Define and implement IP/SoC verification ... plans, build verification test benches to enable IP/sub-system/SoC level verification and develop functional tests based on verification test plan. 2. Collaborate with cross-functional teams like Design, Model, Emulation, and and Silicon validation teams… more
- Meta (Sunnyvale, CA)
- …ensure the optimal performance of our AI Accelerator. **Required Skills:** ASIC Architecture, Runtime Development Responsibilities: 1. Design and develop the host ... runtime environment for heterogeneous computing systems, ensuring efficient communication and data transfer between different processing units 2. Develop and implement device drivers, APIs, and libraries to enable seamless interaction between the host runtime… more
- NVIDIA (Santa Clara, CA)
- …of EDA tool development in the verification field + Hands on experience with ASIC design and verification + Good with C++ and other programming languages like ... Python, Perl, TCL, etc. + Good understanding of computer algorithms. Ways to stand out from the crowd: + Good understanding of Design for Testing including Scan/ATPG/JTAG. + Strong English communication. NVIDIA is widely considered to be one of the technology… more