- Amazon (Cupertino, CA)
- …technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring ... Proficient in programming/scripting languages (Perl, Python, C++) - Solid understanding of ASIC physical design , and methodologies including synthesis, place and… more
- Amazon (Cupertino, CA)
- …emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high ... Qualifications - BS + 8yrs or MS + 6yrs in EE/CS - 6+ years in ASIC Physical Design from - RTL-to-GDSII in either 7nm, 14/16nm, 20nm, or 28nm - Block Design … more
- Cisco (San Jose, CA)
- …in Python for validating functionality, performance, and power metrics + Collaborate with ASIC design team to ensure thorough coverage and test completeness + ... Diagnostics, SDK and BSP). **Key Responsibilities:** + Develop and execute detailed post-silicon validation plans for new ASICs + Design and implement test cases… more
- Cisco (San Jose, CA)
- …are received. **Meet the Team** Cisco Silicon One is the center of Cisco's ASIC design and is driving the development of next-generation network devices for ... Principal Engineer - Silicon One Software Apply (https://jobs.cisco.com/jobs/Login?projectId=1443934) +...design teams to define the next generation of ASIC products being developed. You will work multi-functionally with… more
- Microsoft Corporation (Santa Clara, CA)
- …to CPU-based alternatives Microsoft DPU team in Santa Clara is looking for a Senior Design For Test Engineer to help develop their next generation complex SoCs ... hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data...experience. + 2+ years of industry experience as a Design For Test (DFT) engineer . + Hands… more
- Meta (Sunnyvale, CA)
- …the entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with ... vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips...state of the art IPs or SoCs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with… more
- Meta (Sunnyvale, CA)
- …at the entire stack, through algorithms to architecture, transistors to firmware.As a Design Verification Engineer at Meta's Reality Labs, you will work with ... vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips...state of the art machine learning IPs. **Required Skills:** Design Verification Engineer - Machine Learning Accelerators… more
- Meta (Sunnyvale, CA)
- …stack, from transistor, through architecture, to firmware, and algorithms.As an SoC Physical Design Engineer at Meta Reality Labs, you will perform physical ... needed for our wearable products. **Required Skills:** SoC Physical Design Engineer Responsibilities: 1. Physical design...joining Meta 6. 3+ years of hands-on experience in ASIC physical design with solid understanding of… more
- Cisco (San Jose, CA)
- Senior Analog/mixed-signal IC Design Engineer - Acacia Apply (https://jobs.cisco.com/jobs/Login?projectId=1443040) + Location:San Jose, California, US + ... accuracy, analog designs for optical communications products. We optimize design that will integrate into the ASIC ....for this position reflects the projected hiring range for new hire, full-time salaries in US and/or Canada locations,… more
- Silvus Technologies (Irvine, CA)
- …exciting projects targeted to address challenging real-world communication needs. The _Senior FPGA Design Engineer_ will be based at our new Silvus office, ... THE OPPORTUNITY Silvus is seeking a full-time **_Senior FPGA Design Engineer_** reporting to the _Director of FPGA Engineering_...skill. + Experience with communication systems on FPGA or ASIC designs. **COMPENSATION** _The pay range is NOT a… more