• R&D Engineer Adv Tech Dev

    Broadcom (San Jose, CA)
    …to work with large teams from manufacturing, technology and packaging **Job Description** + Provide design support for IP & ASIC to create robust designs in line ... Silicon manufacturing teams to deploy the technology requirements for ASIC product design & design ...your interest in Broadcom! We are a global technology leader that designs, develops and supplies a broad range… more
    Broadcom (10/29/25)
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  • Senior Timing CAD Engineer, Applied AI

    NVIDIA (Santa Clara, CA)
    …ideally for EDA, semiconductor, or complex data domains + .Strong background in VLSI/ ASIC design - with deep understanding of timing, constraints, STA, or ... is our life's work, to amplify human inventiveness and intelligence. NVIDIA's ASIC -PD Methodology organization is driving the next generation of AI-assisted timing… more
    NVIDIA (11/15/25)
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  • FPGA Engineer, Platforms, Hardware

    Google (Sunnyvale, CA)
    …related field, or equivalent practical experience. + 4 years of experience working in an ASIC or FPGA design technical environment, or 3 years of experience with ... an advanced degree. + Experience with Register-Transfer Level design using Verilog or SystemVerilog. + Experience in the FPGA/ ASIC development lifecycle,… more
    Google (09/28/25)
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  • Senior Research Scientist, Design

    NVIDIA (Santa Clara, CA)
    …this role offers the opportunity to shape that future. What you'll be doing: As a leader in our Design Automation Research Group, you will: + Define and conduct ... methods. + Apply deep learning and GPU computing to improve ASIC and VLSI design tool flows. + Collaborate cross-functionally with circuit design ,… more
    NVIDIA (10/16/25)
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  • Senior Applications Engineer - DDR Design

    Cadence Design Systems, Inc. (San Jose, CA)
    …Scripts* Experience on memory subsystem verification and/or performance analysis* Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and FPGA ... the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San Jose, CAJob DescriptionThe Cadence IP...smart, energetic, collaborative and creative people to help us lead the industry with our IP products. At Cadence,… more
    Cadence Design Systems, Inc. (10/11/25)
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  • Hardware Engineer I (Co-op) - United States

    Cisco (San Francisco, CA)
    …Build and sustain strong relationships with cross-functional teams while collaborating on ASIC Design and Verification for reliable, high-performance products. + ... Team ** Engineering: Open-minded, driven, diverse and deeply creative people at Cisco design the hardware that makes the internet work. Bring your knowledge of… more
    Cisco (11/14/25)
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  • Camera Use Case Tech Lead , Silicon

    Google (San Diego, CA)
    …teams. + Experience with low power architecture and power optimization techniques. + Familiarity with ASIC design flows. **About the job** Be part of a team that ... Camera Use Case Tech Lead , Silicon _corporate_fare_ Google _place_ Mountain View, CA,...Experience with full product delivery cycle (eg, definition, architecture, design and implementation, testing, productization). + Experience working with… more
    Google (11/20/25)
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  • Technical Program Manager, ASIC

    Amazon (San Diego, CA)
    …with engineering leaders ( ASIC /SOC leads) to create project execution plans for ASIC /SOC development considering all criteria to design products the meet the ... ASIC bring-up readiness and test plans. - Work with product/program management lead to ensure that ASIC /SOC development meets schedule, cost, and quality… more
    Amazon (09/21/25)
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  • Senior Silicon Bringup and Test Lead

    Google (Fremont, CA)
    …qualifications:** + 15 years of experience in Application-Specific Integrated Circuit/System on Chip ( ASIC /SoC) design , with a focus on both digital logic ... Senior Silicon Bringup and Test Lead , Raxium - Fremont _corporate_fare_ Google _place_ Fremont,...experience. + 10 years of experience in analog circuit design , including simulation and verification. + Experience working with… more
    Google (11/22/25)
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  • ASIC Engineering Technical Leader

    Cisco (San Jose, CA)
    …that support ATE screening, in-system test, debug and diagnostics needs of the design . + Lead the RTL implementation from the architecture specifications and ... part of the Silicon One development organization as an ASIC implementation engineer in San Jose, CA. As a...generation networking chips. **Your Impact** You will be the lead to drive the DFT/DFx and quality process through… more
    Cisco (11/12/25)
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