- NVIDIA (Santa Clara, CA)
- …tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If you ... intelligence. What You'll Be doing: + As a Front-End ASIC Synthesis Engineer , you will own RTL...and gate level optimization tasks + Collaboration with physical design to address timing, area, congestion tradeoffs + Drive… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Emulation Responsibilities: 1. Deliver high-quality emulation and ... prototyping models on industry-standard emulation and prototyping platforms 2. Design , build, and execute comprehensive emulation test plans to ensure model… more
- Meta (Sunnyvale, CA)
- …DFT EDA tools and IEEE standards (1149, 1500, 1687). **Required Skills:** ASIC Engineer , DFT Responsibilities: 1. Develop and implement DFT strategies ... **Summary:** Meta is hiring ASIC DFT Engineers within our Infrastructure organization to...DFT Engineers within our Infrastructure organization to work on Design for Test (DFT) methodologies, implementation, and… more
- NVIDIA (Santa Clara, CA)
- …solving the most sophisticated problems in everyday life. As a ASIC Verification Engineer at NVIDIA, you will verify the design and implementation of our ... We are now looking for a Senior ASIC Verification Engineer for our Coherent...test /coverage plans, and verify the correctness of the design . This role will collaborate with architects, designers, emulation,… more
- NVIDIA (Santa Clara, CA)
- …NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification. The NVIDIA Clocks Team is ... in SOC and GPU ASIC . The complexity of the clocks and resets design has increased many folds. This requires sophisticated verification to deliver a bug free… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Engineer in the area of DFX ATPG flows and methodologies. Do you like to think creatively and enjoy solving challenges that ... hear from you! What you'll be doing: + Support the deployment of advanced Design -For- Test (DFT) and Automatic Test Pattern Generation (ATPG) solutions + Work… more
- NVIDIA (Santa Clara, CA)
- … tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are ... between frequency and power/area/congestions/yield/etc. + Work on all aspects of DFT/ Test timing such as timing constraints, timing analysis, timing convergence, and… more
- Amazon (San Diego, CA)
- …right silicon solutions, and meeting the power objectives . Create standalone verification test bench to verify the correctness of your block . Work with the ... verification team and participate in System level verification using test benches constructed using UVM, System C and DPI-C . Ensure that the block meets DFT, timing… more
- NVIDIA (Santa Clara, CA)
- …features design requirements to silicon speed characterization needs and test requirements for Productization. + Work alongside system architects, chip and board ... multifaceted, multi-functional team at NVIDIA. We sit at the crossroads of design , architecture, marketing, and productization. Our involvement begins at the arch… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is seeking a highly skilled ASIC Architecture Runtime Development Engineer with experience in hardware modeling, particularly on RISC-V or PCIe ... the reliability and performance of our AI Accelerator. **Required Skills:** ASIC Architecture: Runtime Development Responsibilities: 1. Design and develop… more