- Google (Sunnyvale, CA)
- …Product teams to ensure that goals are met with systems and will work with ASIC /FPGA, Software, and Verification teams to ensure proper verification of ... Staff Hardware Systems Design Engineer, Board and Systems _corporate_fare_ Google _place_...6 years of experience working in a hardware systems design , or 5 years of experience with an advanced… more
- Google (Sunnyvale, CA)
- …or a related field, or equivalent practical experience. + 5 years of experience in logic design , digital ASIC , or SoC design . + Experience with RTL (Register ... innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific… more
- NVIDIA (Santa Clara, CA)
- …GPU-accelerated optimization methods. + Apply deep learning and GPU computing to improve ASIC and VLSI design tool flows. + Collaborate cross-functionally with ... Domain & Technical Expertise: Deep knowledge in EDA/VLSI (eg, synthesis, physical design , verification , timing, reliability, or CAD algorithms) combined with 5+… more
- NVIDIA (Santa Clara, CA)
- …is our life's work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer? If yes, We would love to hear from you! We are looking for a ... Senior Mask Layout Design Engineer, someone who is excited to join a...using Cadence tools. + You'll work cross functionally with ASIC and mixed-signal engineers to customize designs for integration… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Experience on memory subsystem verification and/or performance analysis* Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and FPGA ... an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San Jose, CAJob DescriptionThe Cadence IP team develops industry… more
- Broadcom (San Jose, CA)
- …and high speed clock constraints and specification.** + **Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and ... you apply.** **Job Description:** **Broadcom is looking for a senior level ASIC physical design engineer. In this highly visible role, you will be contributing… more
- NVIDIA (Santa Clara, CA)
- …is our life's work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer? If yes, We would love to hear from you! We are looking for a ... Senior Mask Layout Design Engineer, someone who is excited to join a...technologies using Cadence tools. + You'll work multi-functional with ASIC and mixed-signal engineers to customize designs for integration… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …teams, definers and designers . Write application notes, user guides, articles, design ideas, new product proposals, and evaluation kit manuscripts for internal ... with simulation and synthesis tools . Strong knowledge of ASIC flow, RTL/Verilog . Individual leadership and initiative to...Nice to have : . Experience on memory subsystem verification and/or performance analysis . Knowledge of System Verilog… more
- SanDisk (Milpitas, CA)
- …requirements to various functions of Memory teams to meet systems specs. + Define ASIC requirements for upcoming new NAND Flash based chips and design systems ... products + Work with Architecture and Firmware team on detailed implementation and verification plan. + Monitor NAND readiness and work with Product test teams on… more
- Broadcom (San Jose, CA)
- …blocks and working on initial floor plan. 5). Develop Verilog RTL. design verification support, logic synthesis, physical implementation constraints, static ... excellent academic standing. 2). Must have in-depth knowledge of IC technology, ASIC design flows, EDA tools and Physical design considerations. 3). Thorough… more