• Silicon Validation Engineer, Reality Labs

    Meta (Sunnyvale, CA)
    …highly cross-functional environments - across multiple team sites 14. Experience influencing design , Design Verification and post-silicon validation teams to ... pre-silicon validation platforms (ie, FPGA and emulation) 18. Knowledge of ASIC design flow, silicon foundry test flow, and silicon Firmware development process… more
    Meta (10/22/25)
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  • EDA Workflow Optimization Engineer

    NVIDIA (Santa Clara, CA)
    …full chip design process from inception through study, architecture, design , verification , emulation, layout, packaging, power-on and production. You will ... compute) our chip engineers depend on. + Experience with ASIC , VLSI, CAD/EDA or mixed signal design ...with ASIC , VLSI, CAD/EDA or mixed signal design workflow environments. + Hands-on experience with EDA tools.… more
    NVIDIA (10/03/25)
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  • Senior Component Engineer

    Palo Alto Networks (Santa Clara, CA)
    …of industry best practices for component and product level qualification and design verification testing (DVT practices, HALT, HASS, etc.). + Experience ... component manufacturers to root cause and corrective action implementation and verification . Be the technical point person for component quality/performance issues.… more
    Palo Alto Networks (10/16/25)
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  • Senior Systems Software Engineer - GPU

    NVIDIA (Santa Clara, CA)
    …This role will require extensive collaboration with GPU architects, system architects, ASIC designers and other FW/SW teams to produce world class products. What ... you'll be doing: + Design and implement next-generation NVLink features in C/C++. +...new NVLink platforms from Pre-Silicon to Production + Perform verification , validation, and testing of NVLink-connected products using various… more
    NVIDIA (10/08/25)
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  • DFT Engineer

    Broadcom (San Jose, CA)
    …in Electrical Engineering or Computer Engineering with 10+ years of experience in ASIC DFT development for serial high-speed data center networking. + Experience as ... and constraints generation. + Familiarity with high speed DFT design rules (~2GHz) and multi clock domain architectures.. +...tools to generate verilog and ATE vectors and cross verification . + Experience with GLS and timing analysis. +… more
    Broadcom (11/01/25)
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