- Broadcom (San Jose, CA)
- …to address challenges of designing in deep sub-micron processes and state-of-the-art ASIC design for AI/ computing and networking products **Qualifications : ... years or more experience in a relevant field + Familiarity with VLSI design tools for Place&Route, Verilog simulation, DRC/LVS verification , Timing analysis… more
- Amazon (Cupertino, CA)
- …interconnect & transistor fundamentals in deep sub-micron processes - Understanding of ASIC Physical Design from RTL-to-GDSII - Understanding of other sign-off ... datacenters all around the world. As a Circuit & Design Analysis engineer, you'll collaborate with multiple teams to...activities (ir/em, physical verification , timing closure, DFT) - 3+ years of scripting… more
- NVIDIA (Santa Clara, CA)
- …intelligence. We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior Mask Layout Design Engineer! ... using Cadence tools. + You'll work cross functionally with ASIC and mixed-signal engineers to customize designs for integration...part in floor planning, custom layout and verifying against design rules and schematics. What we need to see:… more
- NVIDIA (Santa Clara, CA)
- …in joining our Dynamic team? If yes, We are looking for a Senior Mask Layout Design Engineer - someone who is excited to join a growing group of diverse individuals ... CMOS technologies using Cadence tools + You'll work with ASIC and mixed-signal engineers to customize designs for integration...will include floor planning, custom layout and verifying against design rules and schematics. What we need to see:… more
- NVIDIA (Santa Clara, CA)
- …is our life's work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer? If yes, We would love to hear from you! We are looking for a ... Senior Mask Layout Design Engineer, someone who is excited to join a...technologies using Cadence tools. + You'll work multi-functional with ASIC and mixed-signal engineers to customize designs for integration… more
- NVIDIA (Santa Clara, CA)
- Are you a Mask Layout Design Engineer who is seeking am amazing opportunity? We are looking for a Senior Mask Layout Design Engineer - someone who is excited to ... state-of-the-art sub-micron CMOS technologies using Cadence tools + You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI… more
- Broadcom (Irvine, CA)
- …with scripting languages to drive automation (Python, Tcl) + Ability to work with ASIC Architects, Designers, and Verification Engineers to: + Create new product ... quality for "first spin" silicon, we in the CSG ASIC team combine production workload-focused test harnesses with large...analysis / troubleshooting + Ability to work with hardware design engineers to capture and analyze digital wave forms… more
- Broadcom (San Jose, CA)
- …Parasitic extraction and simulation, abstract and LEF/DEF generation, LVS/ERC checks, physical verification + Conducting design reviews & creating slides and ... from manufacturing, technology and packaging **Job Description** + Provide design support for IP & ASIC to...release sign off + Provide support for timing, physical verification signoff to make IP & ASIC … more
- Qualcomm (San Diego, CA)
- …with scripting tools and programming languages. * 6+ months of experience with design verification methods. **Principal Duties & Responsibilities:** * Applies ... a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design ...place and route, and timing and power use, and verification or similarly for custom circuit design /layout… more
- SpaceX (Sunnyvale, CA)
- …engineers who can work with world-class cross-disciplinary teams (firmware, architecture, design , validation, product engineering, ASIC implementation). In this ... broadband communication system + Work in close collaboration with ASIC /FPGA, RF/antenna, and software engineers to design ...as TDMA, CDMA and OFDMA + Professional experience in design and verification of high data rate… more
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