- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work on Design for Test ( DFT ) methodologies, implementation, and ... EDA tools and IEEE standards (1149, 1500, 1687). **Required Skills:** ASIC Engineer, DFT Responsibilities: 1. Develop and implement DFT strategies for data… more
- Google (Mountain View, CA)
- …related field, or equivalent practical experience. + 8 years of experience in DFT or physical design. + Experience with scan insertion, Automatic Test Pattern ... (JTAG), Internal JTAG (IJTAG) tools and flow. + Experience with DFT Electronic Design Automation (EDA) Tools like Tessent/Genus/FC/Simvision, etc. **Preferred… more
- Google (Sunnyvale, CA)
- …+ Knowledge of high performance and low-power design techniques. + Knowledge of ASIC Verification, Design For Testing ( DFT ), Synthesis, Static Timing Analysis ... of experience in people management, developing employees. + Experience in ASIC development with System Verilog. + Experience in Computer Architecture, including… more
- NVIDIA (Santa Clara, CA)
- …yield enhancement and spec validation + Partner with other engineering groups including ASIC , DFT , ATE, silicon validation, fab process, software and quality ... teams to coordinate efforts and resolve silicon issues + Initiate and drive process improvements/preventative actions through root cause analysis + The ideal candidate will always look to improve workflows, products, functions and methodologies while working… more
- Broadcom (San Jose, CA)
- …apply.** **Job Description:** Broadcom's ASIC Product Division is seeking candidates for a DFT Manager position at our San Jose Design Center. As a DFT ... Manager, you will lead a group of highly performing DFT Engineers working on delivering high quality custom silicon...customers. The successful candidate will be responsible for leading DFT programs all the way from pre-sales through to… more
- Arrow Electronics (San Jose, CA)
- **Position:** Sr. Director - ASIC Solution Architect **Job Description:** Job Description: **What You'll Be Doing:** + ASIC / Silicon / Semi Engg Solutions for ... clients HQ's in AMER-West + Depth of experience w/ ASIC , Silicon, IP, EDA, RTL to GDS, Verification &...RTL to GDS, Verification & Validation, Physical Design, Test, DFT Engineering Solutions, Turnkey, Managed Services, IP design/engineering +… more
- Cisco (San Jose, CA)
- ASIC Engineering Technical Leader - SDC Apply (https://jobs.cisco.com/jobs/Login?projectId=1434557) + Location:San Jose, California, US + Area of InterestEngineer - ... networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a...fullchip SDCs and work with the Physical Design and DFT teams to close fullchip timing in multiple timing… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end ... (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical...with the Designers to create waivers 6. Perform RTL DFT Analysis and improve the DFT coverage… more
- NVIDIA (Santa Clara, CA)
- …and methodology on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If you are problem ... intelligence. What You'll Be doing: + As a Front-End ASIC Synthesis Engineer, you will own RTL synthesis and...power/area optimization across multiple design blocks + Work with DFT and Verification teams to ensure functional and timing… more
- NVIDIA (Santa Clara, CA)
- …and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are problem ... frequency and power/area/congestions/yield/etc. + Work on all aspects of DFT /Test timing such as timing constraints, timing analysis, timing...to stand out from the crowd: + Experience with DFT timing closure for various modes eg scan shift,… more