- Broadcom (Irvine, CA)
- …leading external and internal cross-functional teams in areas such as physical design, STA, DFT , and packaging? Have you taped out so many chips that you can ... major segments of the Semiconductor industry, including AI. Our ASIC products division is looking for a senior engineer...logic design verification, DRC, logic synthesis + Knowledge of DFT methods including scan, memory BIST and repair **Education… more
- Amazon (Cupertino, CA)
- …scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... integrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/ DFT signal routing - As a key member of...signal routing - As a key member of the ASIC design team, you will implement and deliver high… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... GPUs or Network processor implementation or SOCs. + Understanding of DFT logic and experience with DFT timing closure for various modes eg, scan shift and… more
- NVIDIA (Santa Clara, CA)
- …amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Test Timing Engineer to join our dynamic and growing team. If you want ... such as GPUs, CPUs, DPUs/Network processors, or SOCs + Understanding of DFT logic and experience with DFT timing closure for various modes eg, scan, BIST, etc. +… more
- Meta (Sunnyvale, CA)
- …"Apply to Job" online on this web page. **Required Skills:** ASIC Engineer, Implementation Responsibilities: 1. Run logic/physical synthesis using advanced ... lint and work w/ designers to create waivers. 6. Perform RTL DFT analysis and improve DFT coverage for stuck-at faults. 7. Perform flat and hierarchical clock… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU ... to GPU, CPU and SOC verification team, timing and DFT teams. + Get involved in end-to-end cycle of... teams. + Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes,… more
- NVIDIA (Santa Clara, CA)
- …understanding of ASIC design flow including RTL design and verification, DFT , and ECO. + Strong communication and interpersonal skills are required along with ... the ability to work in a dynamic, global team. NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most brilliant and hardworking people in the world working for us. Are you creative and autonomous? Do… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our dynamic and growing team. If ... flow. + Strong hands-on debugging capability and problem-solving skills. + Background in DFT timing closure for various modes eg scan shift and capture, transition… more
- Amazon (San Diego, CA)
- …benches constructed using UVM, System C and DPI-C . Ensure that the block meets DFT , timing and power targets by working closely with the implementation team . Learn ... about requirements and solutions for systems operating in space . Drive trade-off analysis to benefit customer experience and optimization of resources (costs, power, spectrum) Export Control Requirement: Due to applicable export control laws and regulations,… more
- Amazon (Sunnyvale, CA)
- …by running and tracking results of front-end tools including: Synthesis, Lint (RTL, DFT , UPF), Power Analysis and STA -Take the lead and work with verification ... teams to define functional coverage -Work with pre-silicon verification teams to assist in defining testplans/testbenches -Work with post-silicon validation teams to define and execute on testplans -Write high quality documents to guide and lead a scalable… more