- Cisco (San Jose, CA)
- …production test. 5) Provide technical leadership in Design for Test ( DFT ), scan/ATPG, analog/mixed-signal test, high-speed SERDES bring-up and validation, and defect ... + Multi-functional Collaboration: 1) Partner closely with silicon architecture, ASIC design, verification, software, reliability, manufacturing operations, and product… more
- NVIDIA (Santa Clara, CA)
- …a single chip. Your role will be cross-disciplinary, working with software, ASIC design, verification, physical design, VLSI and platform teams. Our SoC architects ... involves working with other IP architects, designers, verification, Physical Design, Software, DFT , Security, Automotive Safety and others. You will be required to… more
- NVIDIA (Santa Clara, CA)
- …pioneering technologies. Your role will be cross-disciplinary, working with software, ASIC design, verification, physical design, VLSI and platform teams. Our system ... of architecture improvements. + Document architecture specifications; work with ASIC design, software, and VLSI teams to review and...in system level functions such as reset and boot, DFT , and power management + Expertise in analyzing performance… more
- Cisco (San Jose, CA)
- …number of applications are received. Meet The Team You will collaborate with ASIC design teams in the Central Hardware Group, peer Test Engineers in Silicon ... ATE test bring-up. You will partner with the Cisco ASIC team to bring up tests, characterize units, and...* Excellent knowledge of the latest state-of-the-art trends in DFT insertion techniques, including JTAG, Scan, ATPG, SerDes, PCIe… more
- Amazon (Cupertino, CA)
- …scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and ... physical design work. Interface directly with RTL, Physical Design, Package Design, DFT teams to improve methodologies and efficiencies. Be able to independently… more
- NVIDIA (Santa Clara, CA)
- …and implement improvements + You will have the opportunity to influence future ASIC designs to improve test coverage and enable better product yield, test time, ... of relevant experience + Critical thinking, solution focused + Experience with ASIC mixed-signal design, characterization and qualification + Knowledgeable in DFT… more
- Amazon (Cupertino, CA)
- …visualizing QoR/stats - Interface directly with RTL, Physical Design, Package Design, DFT and other teams to improve methodologies and efficiencies and drive efforts ... and sign-of. tools in TCL, Perl, and/or Python - Solid understanding of ASIC physical design, physical design flows, and methodologies including synthesis, place and… more
- Broadcom (San Jose, CA)
- …Verification engineer. In this highly visible role you will be working on ASIC for data center connectivity applications. Qualifications include: + MS or PhD in ... generating UVM RAL model + Prior experience in verification of the DFT design, architecture, and microarchitecture + Proficient with scripting languages like PERL,… more
- NVIDIA (Santa Clara, CA)
- …program management or engineering leadership. + Strong understanding of ASIC /SoC design, verification, bring-up, and productization flows (RTL-to-release). + ... atmospheres. Ways to Stand Out from the crowd: + Background in DFX, DFT , or datacenter-class silicon testability. + Experience with EDA tool data analytics, APIs,… more
- Amazon (Sunnyvale, CA)
- …a Sr. RTL Design Engineer - Wireless Modem within a high performance ASIC design team. This team is using industry leading methodologies to develop proprietary ... constructed using UVM, System C and DPI-C. . Ensure that the block meets DFT , timing and power targets by working closely with the implementation team. . Learn… more