- NVIDIA (Santa Clara, CA)
- …out from the crowd: + Familiarity with Machine Learning/Deep Learning + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Experience ... design implementation and analysis tools + Provide support for ASIC tools and flows + Assist chip design teams...experience; MS preferred + Be familiar with Verilog and ASIC design along with experience in commercial EDA tools… more
- Amazon (Sunnyvale, CA)
- …* Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC /SoCs. * Full chip timing constraints development, full chip / Sub-System STA and ... signoff flow. * Work for Systems and Architecture, SoC Integration, Verification, DFT , Mixed Signal, IP owners, Synthesis, Place & Route and other local/remote… more
- Meta (Sunnyvale, CA)
- …research silicon to demonstrate and integrate advanced IP and AI accelerators into SOC/ ASIC solutions to enable in-system testing and prototyping. The goal is to ... and collaboration skills 9. Knowledge of digital SoC integration and ASIC architecture 10. Skilled in micro-architecture, RTL coding, design verification and… more
- Amazon (Cupertino, CA)
- …scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and ... physical design work. Interface directly with RTL, Physical Design, Package Design, DFT teams to improve methodologies and efficiencies. Be able to independently… more
- Arrow Electronics (San Jose, CA)
- …of design team who oversees **fullchip SDCs** and works with physical design and DFT teams to close **fullchip timing** in multiple timing modes. + Option to also ... in Electrical or Computer Engineering with 7+ years of ASIC or related experience or Master's Degree in Electrical...in Electrical or Computer Engineering with 5+ years of ASIC or related experience. + Experience with **block/full chip… more
- Meta (Sunnyvale, CA)
- …(CTS), routing, static timing analysis and signoff 2. Collaborate with RTL design, DFT , verification, and power teams to ensure seamless integration and secure QOR ... completed prior to joining Meta 6. 3+ years of hands-on experience in ASIC physical design with solid understanding of digital design fundamentals 7. Proficient in… more
- Amazon (Sunnyvale, CA)
- …the RTL/Arch. Teams Basic Qualifications - BS in EE/CS - 7+ years in ASIC Physical Design from RTL-to-GDSII in FINFET technologies such as 5nm/7nm, 14/16nm - ... in extraction of design parameters, QOR metrics, and analyzing trends - Experience with DFT & DFM flows - Ability to provide mentorship, guidance to junior engineers… more
- Broadcom (San Jose, CA)
- …Verification engineer. In this highly visible role you will be working on ASIC for data center connectivity applications. Qualifications include: + MS or PhD in ... generating UVM RAL model + Prior experience in verification of the DFT design, architecture, and microarchitecture + Proficient with scripting languages like PERL,… more
- SanDisk (Milpitas, CA)
- …critical interface between various cross-functional teams, including Test, Reliability, Firmware, ASIC , NAND Design, Operations + Identify and mitigate risks during ... Python scripting for test automation and data analysis + Experience working on DFT and test automation + Hands-on experience with lab equipment (oscilloscopes, logic… more
- Amazon (San Diego, CA)
- …motivated and experienced Post-Silicon Verification Engineer with strong expertise in Digital ASIC and modem (PHY and MAC layer) verification to join our silicon ... PHY/MAC bring-up. * Exposure to firmware-hardware interaction debugging. * Knowledge of DFT /DFD, scan chain, or BIST validation. * Familiarity with signal processing… more