- Meta (Sunnyvale, CA)
- … DFT EDA tools and IEEE standards (1149, 1500, 1687). **Required Skills:** ASIC Engineer , DFT Responsibilities: 1. Develop and implement DFT ... **Summary:** Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work on Design for Test ( DFT ) methodologies, implementation, and… more
- Google (Mountain View, CA)
- …related field, or equivalent practical experience. + 8 years of experience in DFT or physical design. + Experience with scan insertion, Automatic Test Pattern ... (JTAG), Internal JTAG (IJTAG) tools and flow. + Experience with DFT Electronic Design Automation (EDA) Tools like Tessent/Genus/FC/Simvision, etc. **Preferred… more
- Broadcom (San Jose, CA)
- …switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture, to implementation, verification, timing closure, ATE pattern bringup. . You ... you apply.** **Job Description:** Broadcom's CSG division is seeking candidate for a DFT lead position. The successful candidate will be responsible for leading most… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring ... ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At...CMOS analog circuit and physical design + Knowledge of DFT /Scan/MBIST/LBIST and understanding of their impact on physical design… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical ... **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure organization. We...with the Designers to create waivers 6. Perform RTL DFT Analysis and improve the DFT coverage… more
- NVIDIA (Santa Clara, CA)
- …tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If you ... intelligence. What You'll Be doing: + As a Front-End ASIC Synthesis Engineer , you will own RTL...power/area optimization across multiple design blocks + Work with DFT and Verification teams to ensure functional and timing… more
- Cisco (San Jose, CA)
- …aspects of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready ... ASIC Design Engineer - Design &...oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing… more
- NVIDIA (Santa Clara, CA)
- …tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are ... frequency and power/area/congestions/yield/etc. + Work on all aspects of DFT /Test timing such as timing constraints, timing analysis, timing...to stand out from the crowd: + Experience with DFT timing closure for various modes eg scan shift,… more
- Cisco (San Jose, CA)
- ASIC Design Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1441220) + Location:San Jose, California, US + Area of InterestEngineer - Hardware + ... working together to ensure the successful deployment of the ASIC in products. **Your Impact** + Development of high-performance...our design methodology. + Collaborate with the verification, PD, DFT , Package and SW teams to develop next generation… more
- Amazon (Cupertino, CA)
- …scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... integrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/ DFT signal routing - As a key member of...signal routing - As a key member of the ASIC design team, you will implement and deliver high… more