- Cadence Design Systems, Inc. (San Jose, CA)
- …with Cadence EDA tools for Synthesis, Logical Equivalency Checking (LEC), Design-for-Test ( DFT ), Place & Route and Static Timing Analysis (STA).You may get involved ... ideal for someone with several years of hands on ASIC /IC design experience who is looking for a new...an absorbing customer facing role. This role requires strong technical capability in Cadence tools (or similar), flow development,… more
- Amazon (Cupertino, CA)
- …Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help ... scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and… more
- NVIDIA (Santa Clara, CA)
- …yield enhancement and spec validation. + Partner with other engineering groups including ASIC , DFT , ATE, silicon validation, fab process, software and quality ... groundbreaking innovations involving crafting creative solutions for system level diag, verification and post-silicon validation of some of the industry's most… more
- NVIDIA (Santa Clara, CA)
- …yield enhancement and spec validation + Partner with other engineering groups including ASIC , DFT , ATE, silicon validation, fab process, software and quality ... groundbreaking innovations involving crafting creative solutions for system level diag, verification and post-silicon validation of some of the industry's most… more
- Meta (Sunnyvale, CA)
- …(CTS), routing, static timing analysis and signoff 2. Collaborate with RTL design, DFT , verification , and power teams to ensure seamless integration and secure ... obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior… more
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