• Senior E/E & Semiconductor Engineer

    Capgemini (San Jose, CA)
    …data structures, and algorithms. The ideal candidate will have experience in ASIC design and development within Linux-based environments. Proficiency in version ... structures and algorithms to solve complex problems. + Support ASIC design and verification processes. + Develop...combines its broad industry knowledge and cutting-edge technologies in digital and software to support the convergence of the… more
    Capgemini (09/20/25)
    - Related Jobs
  • Senior Mask Design Engineer

    NVIDIA (Santa Clara, CA)
    …is our life's work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer ? If yes, We would love to hear from you! We are looking ... for a Senior Mask Layout Design Engineer , someone who is excited to...mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in groundbreaking sub-micron CMOS… more
    NVIDIA (08/28/25)
    - Related Jobs
  • FPGA Design Engineer

    Tarana Wireless (Milpitas, CA)
    …alongside some of the brightest minds in the industry. If you're passionate about digital design , solving complex problems, and building products that make a ... advanced FPGAs powering our next-gen wireless base stations and ASIC emulation platforms. You'll play a vital role in...logic design experience + Expertise in high-speed digital design + Hands-on experience with Xilinx… more
    Tarana Wireless (09/17/25)
    - Related Jobs
  • Senior Principal Design Verification…

    BAE Systems (San Diego, CA)
    …random, self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL + Experience with FPGA/ ASIC design and verification tools (Mentor Questa or Cadence) + ... required: + Perl/Python + C /Java + Git/Jira/BitBucket + Digital Signal Processing + Matlab/Simulink + Working knowledge of...based on position level and/or job specifics. **Senior Principal Design Verification Engineer - FPGA - (Sign-on… more
    BAE Systems (09/09/25)
    - Related Jobs
  • Senior Mask Design Engineer

    NVIDIA (Santa Clara, CA)
    …We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer , someone who is excited to join a growing and dynamic group of ... for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in state-of-the-art sub-micron CMOS technologies using… more
    NVIDIA (07/16/25)
    - Related Jobs
  • Analog Mixed-Signal Design Engineer

    Broadcom (San Jose, CA)
    …knowledge/experience with TSMC 7nm-5nm, ie understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, ... Engineering or Computer Engineering with 6+ years of high-speed analog mixed signal design in advanced CMOS nodes.** + **Experience in designing low jitter, low… more
    Broadcom (07/11/25)
    - Related Jobs
  • Analog Mixed-Signal Design Engineer

    Broadcom (San Jose, CA)
    …knowledge/experience with TSMC 7nm-5nm, ie understanding of power consumptions, area, estimated design and layout efforts for digital and analog blocks, ... Engineering with 6+ years of high-speed analog mixed signal design in advanced CMOS nodes, or a PhD +...to foundries and solid understanding of supply chain for ASIC product development. + Strong analytical thinking and problem-solving… more
    Broadcom (07/11/25)
    - Related Jobs
  • Senior Technical Lead, Signal/Power Integrity…

    Cisco (San Jose, CA)
    …Service Provider SI team is seeking a Senior Technical Lead, Signal/Power Integrity Engineer for the design and analysis of high-speed interconnects and power ... structures. + Perform pre- and post-route signal integrity analysis of both PCB and ASIC package designs. + Write signal integrity design guidelines, test plans,… more
    Cisco (10/03/25)
    - Related Jobs
  • Signal Integrity Engineer

    Cisco (San Jose, CA)
    …the Team** The Cisco Service Provider SI team is seeking a Signal Integrity Engineer for the design and analysis of high-speed components, interfaces, and power ... Signal Integrity Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1450913) + Location:San Jose, California, US...Switch products, be a part of the definition and design of current and next generation ASIC ,… more
    Cisco (10/03/25)
    - Related Jobs
  • Principal Engineer , Systems Design

    SanDisk (Milpitas, CA)
    …Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we're living in and that we have the power to shape. Sandisk ... of Memory teams to meet systems specs. + Define ASIC requirements for upcoming new NAND Flash based chips...requirements for upcoming new NAND Flash based chips and design systems algorithms. + Develop and maintain a System… more
    SanDisk (09/20/25)
    - Related Jobs