- NVIDIA (Santa Clara, CA)
- …and intelligence. We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior Mask Layout Design ... for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in state-of-the-art sub-micron CMOS technologies using… more
- Qualcomm (San Diego, CA)
- …performance, power and area. The successful candidate will possess in-depth understanding of ASIC design flow and the challenges posed by advanced deep ... Engineering Group > GPU ASICS Engineering **General Summary:** The Design Implementation Engineer will work in Qualcomm's...Science, Engineering or closely related field + Experience with digital design and RTL development, + Experience… more
- Qualcomm (Santa Clara, CA)
- …develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL design ... should be willing to work in cross-collaborative environment + Strong experience in design automation using TCL/Perl/Python. + Familiar with digital flow … more
- Tarana Wireless (Milpitas, CA)
- …alongside some of the brightest minds in the industry. If you're passionate about digital design , solving complex problems, and building products that make a ... advanced FPGAs powering our next-gen wireless base stations and ASIC emulation platforms. You'll play a vital role in...logic design experience + Expertise in high-speed digital design + Hands-on experience with Xilinx… more
- NVIDIA (Santa Clara, CA)
- …We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer , someone who is excited to join a growing and dynamic group of ... for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in state-of-the-art sub-micron CMOS technologies using… more
- BAE Systems (San Diego, CA)
- …random, self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL + Experience with FPGA/ ASIC design and verification tools (Mentor Questa or Cadence) + ... required: + Perl/Python + C /Java + Git/Jira/BitBucket + Digital Signal Processing + Matlab/Simulink + Working knowledge of...based on position level and/or job specifics. **Senior Principal Design Verification Engineer - FPGA - (Sign-on… more
- Qualcomm (Santa Clara, CA)
- …As a Qualcomm ASIC Engineer , you will define, model, design ( digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) ... in Science, Engineering, or related field and 6+ years of ASIC design , verification, validation, integration, or related work experience. OR Master's degree… more
- Broadcom (Irvine, CA)
- …Trace buffer and post-mortem analysis / troubleshooting + Ability to work with hardware design engineers to capture and analyze digital wave forms + Additional / ... quality for "first spin" silicon, we in the CSG ASIC team combine production workload-focused test harnesses with large...looking for a Sr. level system software / firmware engineer , with broad experience developing software and firmware for… more
- Siemens (Fremont, CA)
- …direction of our RTL Synthesis product development, focus on delivering cutting-edge solutions for digital ASIC design . The ideal candidate brings 10+ years ... design and technical direction for RTL synthesis tools within the digital ASIC design flow. Define and evolve the architecture of RTL synthesis… more
- Qualcomm (San Diego, CA)
- …Modem, Machine learning, IoT and Automotive. This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by ... low power design **Keywords** RTL, processor, Verilog, System Verilog, logic design , digital design , processor integration, bus interface, cache.… more