- NVIDIA (Santa Clara, CA)
- …now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software solutions ... logic analyzers and/or other silicon visibility tools. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis… more
- NVIDIA (Santa Clara, CA)
- …standard FPGA prototyping platforms. We are now looking for a Senior FPGA Prototyping Engineer to join our Emulation team onsite in Santa Clara, CA. What you'll be ... on Synopsys Protocompiler or Synplify Premier and Xilinx Vivado + Exposure to ASIC design and verification tools (VCS or equivalent, Verdi, GDB). + Knowledge of… more
- Two95 International Inc. (Sunnyvale, CA)
- Hi, Title: Lead / Senior Verification engineer Location: San Jose, CA / Santa Clara, CA Duration: 6+ Months Rate: $Open Skills: UVM and System Verilog Requirement:. ... * 5+ or more years of proven experience on ASIC / SoC / IP Verification. * Strong experience in SystemVerilog and UVM verification methodologies * Proficiency in… more
- Amazon (San Diego, CA)
- …around the world. We are seeking a highly motivated and experienced Post-Silicon Verification Engineer with strong expertise in Digital ASIC and modem (PHY and ... MAC layer) verification to join our silicon engineering team. The ideal candidate will work on validating complex SoC designs and wireless modem subsystems in a post-silicon lab environment, ensuring high performance, robustness, and compliance with industry… more
- Amazon (Cupertino, CA)
- …AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our ... and sign-of. tools in TCL, Perl, and/or Python - Solid understanding of ASIC physical design, physical design flows, and methodologies including synthesis, place and… more
- NVIDIA (Santa Clara, CA)
- …We are seeking an innovative senior timing signoff and constraint methodology engineer to develop pioneering timing sign-off strategies for next-generation GPUs and ... equivalent experience) in Electrical or Computer Engineering with 4+ years' experience in ASIC Design and Timing. + Expertise in Primetime and timing constraints +… more
- Tarana Wireless (Milpitas, CA)
- …and testing of advanced FPGAs powering our next-gen wireless base stations and ASIC emulation platforms. You'll play a vital role in building the foundation of ... tomorrow's wireless infrastructure. What You'll Do: + Design, implement, and debug logic for large FPGAs + Simulate, test, and validate logic at both module and system levels + Participate in system-level integration and troubleshooting + Collaborate across… more
- Western Digital (Roseville, CA)
- …product development cycle + Works closely with the other system test, hardware, ASIC and firmware engineers to improve test methodology and develop new tests and ... new strategies + Configures customer hardware and software systems; troubleshoot problems to get to root cause + Maintains customer and test equipment to current revision **Qualifications** **REQUIRED:** + Bachelors degree or Masters degree in Engineering,… more
- NVIDIA (Santa Clara, CA)
- …CPUs. NVIDIA's robust partner ecosystem enables hyperscalers to build an ASIC hybrid AI infrastructure with NVIDIA NVLink, rack-scale architecture. We're searching ... for a highly motived, technical architect to champion work across NVIDIA's Software, Architecture, Networking and Systems engineering teams in defining the architecture for NVLink Fusion. Ensuring we have seamless integration of partner ASICs/CPUs into our… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …related experience in design and EDA (Digital Implementation/Signoff) + Understands ASIC Design implementation process and steps + Strong hands-on experience with ... Place & Route (Innovus, ICC2, Fusion Compiler) + Exposure and experience with Synthesis (Genus, RTL Compiler, Design Compiler) + Experience with EDA tools in the IC digital implementation & signoff flows (STA tools) + Strong STA and SDC debugging abilities are… more