- Meta (Sunnyvale, CA)
- …click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Leverage Design Verification ... Post-Silicon teams towards creating a first-pass silicon success. 5. Furthermore, the ASIC Engineer , Design Verification will define and implement IP/SoC… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....physical design of an end-to-end IP or integration of ASIC /SoC design and point out lower power and higher… more
- Google (San Diego, CA)
- Senior ASIC Engineer , IP Design, Silicon _corporate_fare_ Google _place_ Mountain View, CA, USA; San Diego, CA, USA **Mid** Experience driving progress, solving ... like Python or Perl. + Experience with ARM-based SoCs, interconnects and ASIC methodology. **Preferred qualifications:** + Master's degree or PhD in Electrical… more
- Meta (Sunnyvale, CA)
- …as machine learning, video transcoding and network acceleration. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such… more
- NVIDIA (Santa Clara, CA)
- …a lasting impact on the world! We are now looking for an Low Power Design/Verification ASIC Engineer - New College Grad 2026. We continue to rapidly grow the ... research and development of energy-efficient GPU and SOC architectures. We are continually innovating in creative and unrivaled ways to improve our ability to deliver exceptional perf/watt solutions in a wide range of sectors. Come join NVIDIAs Low Power DV… more
- Meta (Sunnyvale, CA)
- …click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced ... optimization techniques and generate optimized gate level netlist for Timing, Area, and Power. 2. Debug timing/area/congestion issues and resolve w/ RTL & physical designers. 3. Perform power estimation at RTL & gate level and identify power reduction… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... team, timing and DFT teams. + Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and… more
- SpaceX (Irvine, CA)
- Sr. ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... with the ultimate goal of enabling human life on Mars. SR. ASIC DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building… more
- Meta (Sunnyvale, CA)
- …apply, click "Apply to Job" online on this web page. **Required Skills:** ASIC Verification Engineer Responsibilities: 1. Develop and execute verification plans ... for ASIC designs, ensuring comprehensive coverage and validation of design...4. SystemVerilog, UVM). 5. Perform simulation and debugging of ASIC designs to identify and resolve functional issues. 6.… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC/ ASIC DFT Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building… more