• Sr. Physical Design Methodology Engineer

    Amazon (Cupertino, CA)
    …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new ... in programming/scripting languages (Perl, Python, C++) - Solid understanding of ASIC physical design, and methodologies including synthesis, place and route, STA,… more
    Amazon (10/25/25)
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  • Design Implementation Engineer

    Broadcom (San Jose, CA)
    …Candidate will work closely with the IP and SOC design teams to enable block and ASIC level timing closure. + The engineer will work with the internal ASIC ... mixed signal IP blocks used in the development of Broadcom's ASIC / SoC products. Activities include constraints development, constraints verification, deployment… more
    Broadcom (11/20/25)
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  • ASIC Design Technical Leader - Design…

    Cisco (San Jose, CA)
    …service provider networks. Cisco's silicon team offers a unique experience for ASIC engineers, combining the resources and stability of a large, multi-geography ... of a smaller, startup-style team. You'll collaborate with exceptional talent with deep ASIC design and development expertise. As part of a systems company, you'll… more
    Cisco (11/18/25)
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  • Senior Custom ASIC Engineering Lead

    Broadcom (Irvine, CA)
    …industry, including AI. Our ASIC products division is looking for a senior engineer to guide Customer teams designing challenging chips in areas such as AI, HPC, ... Sign-In before you apply.** **Job Description:** Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas such… more
    Broadcom (11/06/25)
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  • Senior Memory System Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is now looking for a Senior Memory System Engineer to join our ASIC Memory Subsystem team! As a Senior Systems Engineer at NVIDIA, you'll join a group ... RAS in memory for Next generation SOC and Systems. + Collaborate with ASIC Architects, Designers, Software and Firmware SW/FW teams to drive memory technology and… more
    NVIDIA (10/02/25)
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  • Sr. Full Chip Physical Design Engineer

    SpaceX (Sunnyvale, CA)
    Sr. Full Chip Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring ... goal of enabling human life on Mars. SR. FULL CHIP PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and… more
    SpaceX (11/14/25)
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  • Chip Integration Engineer

    Broadcom (San Jose, CA)
    …Group at Broadcom has brought some of the most complex and cutting-edge networking ASIC 's and multichip solutions to market over the last decade. The group develops ... ASIC 's for L2/L3 switch routing. These products support the...of the order of several hunards Terabits/sec. These networking ASIC 's support a large number of ports ranging from… more
    Broadcom (11/19/25)
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  • Signal Integrity Engineer

    Cisco (San Jose, CA)
    **Signal Integrity Engineer ** The application window is expected to close 1/12/2026. The job posting may be removed earlier if the position is filled or if a ... Service Provider SI team is seeking a Signal Integrity Engineer for the design and analysis of high-speed components,...the definition and design of current and next generation ASIC , package, printed circuit board (PCB), and system interconnect.… more
    Cisco (11/12/25)
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  • Hardware Engineer

    Meta (Menlo Park, CA)
    **Summary:** Meta is seeking a versatile Hardware Engineer to join our Compute Hardware team. Our mission is backed by a massive hardware infrastructure. Our ... cutting-edge data centers affecting billions of users. **Required Skills:** Hardware Engineer Responsibilities: 1. Work with local and remote teams and suppliers,… more
    Meta (10/16/25)
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  • Senior Timing Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... experience) in Electrical or Computer Engineering with 3 years' experience in ASIC Design and Timing. + Good understanding of modeling circuits for sign-off… more
    NVIDIA (11/20/25)
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