• Cyber Systems Security Engineer Staff…

    Lockheed Martin (Fort Worth, TX)
    **Description:** The Cyber Systems Security Engineer Stf will be responsible for designing, assembly, integration, and maintenance of System Integration Lab \(SIL\), ... storage solutions and servers * Familiarity with embedded systems such as ASIC or FPGA based computing * Strong technical understanding of architecture, design… more
    Lockheed Martin (07/26/25)
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  • Quality & Reliability Engineer , Annapurna…

    Amazon (Austin, TX)
    …generation of our cloud infrastructure with cutting edge technologies for machine learning, from ASIC Si chip to servers. As a quality and reliability engineer ... in the team, you will work closely with other teams and vendors to ensure that the quality and reliability of our product meet our high standards and the customer requests, from the design stage all the way to the production. This will include conducting risk… more
    Amazon (07/22/25)
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  • Senior Principal Design Verification…

    BAE Systems (Austin, TX)
    …self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL + Experience with FPGA/ ASIC design and verification tools (Mentor Questa or Cadence) + Proven ... based on position level and/or job specifics. **Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)** **114362BR** EEO Career Site Equal… more
    BAE Systems (07/11/25)
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  • Sr. System Development Engineer

    Amazon (Austin, TX)
    …in the world! Key job responsibilities As a systems development engineer you will build Cloud-Scale Machine Learning Acceleration Infrastructure including ... performance compute clusters, infrastructure automation of hardware/software/firmware testing, and ASIC /EDA development. You will help scale the next generation of… more
    Amazon (06/27/25)
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  • Senior Post Silicon Engineer

    Amazon (Austin, TX)
    …to unserved and underserved communities around the world. As a Senior Post Silicon Engineer , you will be a critical member of a high-performance team responsible for ... of work experience in Bring Up, Validation and characterization of SOC or ASIC * Proficient in characterizing PLL performance through metrics like jitter, phase… more
    Amazon (06/14/25)
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  • Embedded Physical Layer SW Engineer

    Amazon (Austin, TX)
    …to unserved and underserved communities around the world. As a Modem Software Design Engineer you will be a part of the team participating in the definition of ... for broadband satellite communication modem systems. - Work closely with ASIC , communication systems and software teams to support system bring-ups, end-to-end… more
    Amazon (06/11/25)
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  • System Development Engineer II,…

    Amazon (Austin, TX)
    …in the world! Key job responsibilities As a systems development engineer you will build Cloud-Scale Machine Learning Acceleration Infrastructure including ... performance compute clusters, infrastructure automation of hardware/software/firmware testing, and ASIC /EDA development. You will help scale the next generation of… more
    Amazon (06/11/25)
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  • Sr. Embedded PHY SW Engineer , Wireless…

    Amazon (Austin, TX)
    …unserved and underserved communities around the world. As a Senior Modem Software Design Engineer you will be a part of the team participating in the definition as ... communications between the L1 and L2 software stacks. - Work closely with ASIC design, Verification and MAC systems and software teams to support board bring-up,… more
    Amazon (06/11/25)
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  • Physical Design Methodology Engineer

    Amazon (Austin, TX)
    …AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our ... and sign-of. tools in TCL, Perl, and/or Python - Solid understanding of ASIC physical design, physical design flows, and methodologies including synthesis, place and… more
    Amazon (06/03/25)
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  • CPU Physical Design Timing Engineer

    Qualcomm (Austin, TX)
    …CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL design team to develop timing ... noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, + Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus) + Expert… more
    Qualcomm (06/03/25)
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