• Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer . NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... networks and/or caches. + Great understanding of ASIC design flow including RTL design , verification , logic synthesis and timing analysis. + Exposure… more
    NVIDIA (09/09/25)
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  • ASIC Engineer , Physical…

    Meta (Sunnyvale, CA)
    …efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our...synthesis, static timing analysis, IR drop, EM, and physical verification in advanced technology nodes 2. Resolve design more
    Meta (11/05/25)
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  • Sr. ASIC Design Engineer

    Amazon (Cupertino, CA)
    design quality and making the right trade-offs. Key job responsibilities As an ASIC Design Engineer , you will: * Develop and implement high-performance, ... massive scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and… more
    Amazon (09/13/25)
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  • Senior ASIC Verification

    NVIDIA (Santa Clara, CA)
    …+ 5+ years of verification experience + Exposure to Computer Architecture, ASIC design and verification methodology is required + Strong ability ... NVIDIA is seeking best-in-class ASIC Verification Engineers to verify the...design are verifiable + Architect and plan the verification strategy and execution for sub-system features impacting your… more
    NVIDIA (10/10/25)
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  • ASIC Design Engineer

    Amazon (Cupertino, CA)
    …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and ... signal routing - As a key member of the ASIC design team, you will implement and...design . - Work with with architects, other designers, verification teams, pre- and post-silicon validation teams, synthesis, timing… more
    Amazon (10/31/25)
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  • ASIC Design Engineer - New…

    NVIDIA (Santa Clara, CA)
    NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA, you'll join a group of ... to be responsible for the micro-architecture and design including RTL design , synthesis, functional verification and timing analysis using innovative CAD… more
    NVIDIA (10/29/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... DFT teams. + Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation,...to collaborate with multiple teams. + Experience in RTL design (Verilog), verification and logic synthesis. +… more
    NVIDIA (10/28/25)
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  • Senior Reset and Boot ASIC Engineer

    NVIDIA (Santa Clara, CA)
    …Reset and Boot. + Collaborate with architects, ASIC designers, and verification engineers to design sophisticated system-level modules such as Floorsweep, ... NVIDIA is looking for a Senior Reset and Boot ASIC Engineer to join our System ...doing: + Be an integral part of the System ASIC Design team to help with the… more
    NVIDIA (09/30/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... NVIDIA's next generation GPUs + Partner with RTL and Design Verification engineers to ensure delivery meets...ASIC design flow including front end design and verification , DFT, and timing analysis… more
    NVIDIA (08/27/25)
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  • ASIC Engineer , Power

    Meta (Sunnyvale, CA)
    …To apply, click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Power Responsibilities: 1. Develop power vectors for estimation and ... optimization. 2. Low-power design of ASIC modules. 3. Run industry...estimation, analysis and optimization at various stages of the design 19. UPF generation, verification (VC Low… more
    Meta (10/26/25)
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