- Arrow Electronics (Mountain View, CA)
- **Position:** Design Verification Engineer **Job Description:** Principal Accountabilities * Responsible for architecting Verification Environment for ... ASIC SoC and providing verification support from defining verification plan to...plan to multi-million gate product tapeout & for Test design and development * Develop complex self checking test… more
- NVIDIA (Santa Clara, CA)
- …cycles, this is your place to be. This role specifically requires a skilled ASIC Verification Engineer with expertise in cache coherency protocols and ... NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify the next... methodologies. What you'll be doing: + Responsible for ASIC design verification for various… more
- Butler America (Sunnyvale, CA)
- FPGA Design / Verification Engineer Location: Sunnyvale, CA Job ID: #71390 Pay Range: $75-90 The selected candidate will be responsible for ASIC & FPGA ... provide support and technical direction to junior engineers. Overall contribution to design , simulation, verification , integration & test of complex, high speed… more
- US Tech Solutions (Goleta, CA)
- …assigned verification tasks. **Experience:** + 5-8 years of experience in Pre-Silicon Design Verification (FPGA or ASIC ). + Strong proficiency in ... **Job Description:** + The Verification Engineer will contribute to the...verification deliverables within a UVM/SystemVerilog environment. + The engineer will collaborate with design , architecture, and… more
- Meta (Sunnyvale, CA)
- …stack, from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and ... 2. Develop functional tests based on verification test plan 3. Drive Design Verification to closure based on defined verification metrics on test… more
- BAE Systems (San Diego, CA)
- …may be available based on position level and/or job specifics. **Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)** **117193BR** ... self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL + Experience with FPGA/ ASIC design and verification tools (Mentor Questa or Cadence) +… more
- SpaceX (Sunnyvale, CA)
- Sr. Full Chip Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... the ultimate goal of enabling human life on Mars. SR. FULL CHIP PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in… more
- Google (Sunnyvale, CA)
- Physical Design Flow and Methodology Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and ... computer architecture. + 10 years of experience in physical design flow and methodologies for high-performance ASIC /SoC...(eg, STARRC). + Ability to develop and deploy repeatable design methodologies, focusing on low-power verification . +… more
- Broadcom (San Jose, CA)
- …guidelines **Knowledge and Experience required:** + A good understanding of IP & ASIC design methodologies + Extensive experience with EDA DRC/LVS support + ... already have a Candidate Account, please Sign-In before you apply.** **Job Description:** ** Design Automation Engineer ** This position is part of a team tasked… more
- NVIDIA (Santa Clara, CA)
- …we need to see: + BS / MS or equivalent experience. + 3+ years of ASIC verification experience of complex design units displaying good attention to detail, ... NVIDIA is seeking hardworking, motivated and creative Senior Verification Engineer for our Tegra SoC...Background with System Verilog and UVM based methodology for ASIC verification . Ways to stand out from… more