- NVIDIA (Santa Clara, CA)
- …is our life's work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer ? If yes, We would love to hear from you! We are looking ... for a Senior Mask Layout Design Engineer , someone who is excited to...using Cadence tools. + You'll work cross functionally with ASIC and mixed-signal engineers to customize designs for integration… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Experience on memory subsystem verification and/or performance analysis* Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and FPGA ... to make an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San Jose, CAJob DescriptionThe Cadence IP team develops… more
- NVIDIA (Santa Clara, CA)
- …is our life's work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer ? If yes, We would love to hear from you! We are looking ... for a Senior Mask Layout Design Engineer , someone who is excited to...technologies using Cadence tools. + You'll work multi-functional with ASIC and mixed-signal engineers to customize designs for integration… more
- NVIDIA (Santa Clara, CA)
- …analyzers and/or other silicon visibility tools. + Great understanding of ASIC design flow including RTL design , verification , logic synthesis, timing ... Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement...teams at NVIDIA. + Work closely with software, architecture, design , verification , and silicon validation teams. +… more
- Google (Sunnyvale, CA)
- Design Engineer , Low Power, RTL, ML Accelerators...practical experience. + 5 years of experience in logic design , digital ASIC , or SoC design . ... innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific… more
- Broadcom (San Jose, CA)
- …Sign-In before you apply.** **Job Description:** **Broadcom is looking for a senior level ASIC physical design engineer . In this highly visible role, you ... and high speed clock constraints and specification.** + **Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Join the High-Performance Culture at Cadence. As a Lead Technical Presales Engineer , you will use your knowledge of different memory interface standards to ... teams, definers and designers . Write application notes, user guides, articles, design ideas, new product proposals, and evaluation kit manuscripts for internal… more
- SanDisk (Milpitas, CA)
- …requirements to various functions of Memory teams to meet systems specs. + Define ASIC requirements for upcoming new NAND Flash based chips and design systems ... products + Work with Architecture and Firmware team on detailed implementation and verification plan. + Monitor NAND readiness and work with Product test teams on… more
- Broadcom (San Jose, CA)
- …Candidate Account, please Sign-In before you apply.** **Job Description:** **Principal DFT Engineer ** Broadcom's ASIC Product Division is seeking candidates for ... way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production. The candidate would… more
- Meta (Menlo Park, CA)
- …issues **Preferred Qualifications:** Preferred Qualifications: 10. 6+ years of experience with designing ASIC verification & bring up hardware 11. 6+ years of ... **Summary:** Meta is seeking a versatile Hardware Engineer to join our Compute Hardware team. Our...suppliers, to define product roadmap and program 2. Specify, design , and develop CPU/GPU/ ASIC based compute hardware… more