• ASIC Verification Engineer

    Amazon (Austin, TX)
    …digital verification , preferably in areas of image processing. - Familiarity with formal verification techniques - Lab debug experience and/or FPGA debug - ... highly differentiated silicon into Blink and Ring battery powered devices. Our verification team works on state-of-the art SoCs in a vertically integrated team… more
    Amazon (03/05/25)
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  • ASIC Engineer , Design

    Meta (Austin, TX)
    …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...in HLS 17. Experience with Synthesis, Timing Closure and Formal Verification Methodology 18. Experience with Power… more
    Meta (03/12/25)
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  • ASIC Implementation Engineer

    Meta (Austin, TX)
    …Estimation at RTL and Gate Level and identify power reduction opportunities. 4. Run Formal Verification checks between RTL and Gate level netlist and debug the ... on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical… more
    Meta (04/18/25)
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  • ASIC Implementation Engineer

    Meta (Austin, TX)
    …Estimation at RTL and Gate Level and identify power reduction opportunities. 4. Run Formal Verification checks between RTL and Gate level netlist and debug the ... on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical… more
    Meta (04/16/25)
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  • ASIC Engineer , Design

    Meta (Austin, TX)
    …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...Peripheral Subsystems 12. Experience with Synthesis, Timing Closure and Formal Verification Methodology 13. Master's or PhD… more
    Meta (04/04/25)
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  • ASIC Engineer

    Meta (Austin, TX)
    …apply, click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer Responsibilities: 1. Participate in Micro-architecture, Design, and ... Synthesis, & Power Optimization 13. 5. Synthesis, Timing Closure or Formal Verification Methodology 14. 6. TCL, Python, Perl, or Shell-scripting **Public… more
    Meta (03/15/25)
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  • Sr. ASIC Design Engineer , Project…

    Amazon (Austin, TX)
    …Familiarity with UVM and Matlab . Ability to write assertions and exposure to Formal verification Amazon is an equal opportunity employer and does not ... blocks . Perform initial synthesis & timing analysis . Assist verification team in unit verification including test plan development . Assist with debug and… more
    Amazon (02/13/25)
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  • Silicon Verification Engineer

    ManpowerGroup (Austin, TX)
    …Austin, TX **What's the Job?** + Focus on verifying the design of the ASIC /SoC using simulation, formal verification , and emulation. + Utilize tools ... a leader in technology innovation, is seeking a Silicon Verification Engineer to join their team. As...digital design principles and computer architecture. + Experience with formal verification tools and methodologies. **What's in… more
    ManpowerGroup (02/19/25)
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  • Design Verification Engineer

    Meta (Austin, TX)
    …entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with a ... of the art IPs or SoCs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with researchers...or more of the following areas along with functional verification - SV Assertions, Formal , Emulation. 11.… more
    Meta (02/12/25)
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  • Physical Design Engineer

    Qualcomm (Austin, TX)
    …timing fixes and functional ECOs, debugging and fixing physical violations, and formal verification . The individual also should have deep knowledge on ... Compiler - Timing closure experience in Synopsys PTSI - Formal verification experience - Power domain analysis...Science, Engineering, or related field and 6+ years of ASIC design, verification , validation, integration, or related… more
    Qualcomm (04/28/25)
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