- Meta (Olympia, WA)
- **Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Formal Verification Responsibilities: 1. Provide… more
- Amazon (Redmond, WA)
- …in the validation of ASIC implementations in Verilog/SystemVerilog . Run formal verification of complex blocks to ensure functional correctness . Work ... Matlab model : development or DV integration experience - Familiarity with formal verification techniques - Strong written and verbal skills Amazon is an equal… more
- Capgemini (Seattle, WA)
- **Job Description:** We are seeking a SoC Design Verification Engineer to join our team 100% onsite in either Seattle, WA or Santa Clara, CA. The ideal candidate ... areas in addition to functional verification : + SystemVerilog Assertions (SVA) + Formal Verification + Emulation + Experience with EDA tools and scripting… more
- Meta (Redmond, WA)
- …from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement ... plans, and build test benches for block, IP, sub-system, and SoC level verification 2. Develop functional tests based on verification test plan 3. Drive… more
- Microsoft Corporation (Redmond, WA)
- …across Microsoft cloud hardware. We are seeking a motivated **Senior** ** Verification Engineer ** who is enthusiatic about cutting-edge hardware acceleration ... experience. + 3 years of developing UVM-based testbenches or completion of formal design verification (DV) training. **Other Requirements:** Ability to meet… more