- Meta (Sunnyvale, CA)
- …this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced optimization ... and corresponding reset sequence for RDC. 10. Develop timing constraints for RTL- synthesis and PrimeTime-STA for blocks and top-level including SOC. 11. Analyze… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior Reset and Boot ASIC Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our ... Make the choice to join us today. With the System- ASIC team, you will contribute to designing multiple products...The team is also handling the architecture, design, and synthesis of multiple System-level modules. What you'll be doing:… more
- SpaceX (Irvine, CA)
- …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. ASIC Design Engineer (Silicon Engineering) Irvine,...timing constraint for those IPs and support the physical implementation team ( synthesis , timing closure, formality check)… more
- SpaceX (Sunnyvale, CA)
- …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... ASIC /SOC DFT Engineer (Silicon Engineering) Sunnyvale,...within Subsystems + Running and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and… more
- RTX Corporation (El Segundo, CA)
- …the verification of RTL blocks using VHDL or System Verilog. + Proficiency using ASIC and/or FPGA simulation and synthesis tools (eg Modelsim, Synplify, Quartus, ... or Computer engineering candidate to be involved in the design, implementation , verification, and integration of a wide variety of high-performance digital… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... full chip level. + Help in driving frontend and backend implementation including synthesis , equivalence checking, floor-planning, timing constraints, timing… more
- NVIDIA (Santa Clara, CA)
- …amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... including clock domain crossing checks and MTBF analysis, logic synthesis , netlist quality checks, etc. + Help in all...timing constraints generation and management, and ECO generation and implementation . What we need to see: + BS (or… more
- NVIDIA (Santa Clara, CA)
- …Make the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects ... DFT teams. + Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation ,...+ Experience in RTL design (Verilog), verification and logic synthesis . + Strong coding skills in python or other… more
- Meta (Sunnyvale, CA)
- …as machine learning, video transcoding and network acceleration. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...in test plan development and debug 4. Collaboration with implementation team to close the design on timing and… more