- Meta (Sunnyvale, CA)
- …prior to joining Meta 8. 2+ years of experience as a Digital Design Engineer 9. Experience in RTL coding, synthesis and/or SoC Integration 10. Experience ... **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work...for top-level or block level uArchitecture definition and RTL implementation 2. Contribute to chip-level integration, verification plan development… more
- NVIDIA (Santa Clara, CA)
- Are you passionate about DGX system connecting multiple ASIC chips together and FPGA prototyping? Are you interested in pushing the boundaries of innovation to make ... We are now looking for a Senior Systems Prototyping Engineer to join our Emulation team onsite in Santa...RTL FPGA-friendly, partitioning the design and taking it through synthesis and place and route. + Improve performance of… more
- Broadcom (San Jose, CA)
- …Candidate Account, please Sign-In before you apply.** **Job Description:** **Principal DFT Engineer ** Broadcom's ASIC Product Division is seeking candidates for ... programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production. The… more
- Meta (San Diego, CA)
- **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design ... virtual and augmented reality systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block level uArchitecture… more
- Amazon (Cupertino, CA)
- …tool decisions. - Experience in high-performance, low-power physical design, and implementation techniques with industry standard synthesis , PnR, or Signoff ... our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud...years in developing design methodology or CAD flows in synthesis , PNR, or sign-off areas for advanced technology nodes.… more
- NVIDIA (Santa Clara, CA)
- …and last-level caches , working closely with the physical design team on implementation , synthesis and timing closure as well as working on micro-architectural ... We are now looking for a Logic Design Engineer with Physical Design background! As a member...ASIC design flow including RTL design, verification, logic synthesis , prototyping, DFT, timing analysis, floor-planning, ECO, bring-up &… more
- Silvus Technologies (Los Angeles, CA)
- …career._ THE OPPORTUNITY Silvus is seeking a **_Principal FPGA / RTL Design Engineer - Signal Processing_** who will report to the _Director of FPGA Engineering_ on ... field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking… more
- Silvus Technologies (Irvine, CA)
- …career._ THE OPPORTUNITY Silvus is seeking a full-time Principal FPGA / RTL Design Engineer who will report to the Senior Engineering Director for Irvine and work ... field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking… more
- Silvus Technologies (Irvine, CA)
- …field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking ... engineers. + RTL coding, simulation, and test bench development. + FPGA synthesis and timing closure. + Hardware verification and troubleshooting; familiarity with… more
- Silvus Technologies (Los Angeles, CA)
- …field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking ... engineers. + RTL coding, simulation, and test bench development. + FPGA synthesis and timing closure. + Hardware verification and troubleshooting; familiarity with… more
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