- Silvus Technologies (Los Angeles, CA)
- …career._ THE OPPORTUNITY Silvus is seeking a **_Principal FPGA / RTL Design Engineer - Signal Processing_** who will report to the _Director of FPGA Engineering_ on ... field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking… more
- Broadcom (San Jose, CA)
- …TCM, Tempus) and scripting languages (eg, Tcl, Perl). + Proficiency in using synthesis tools (Genus) + Strong understanding of ASIC design flows, including ... Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role, you will be...Tcl or Perl. + Provide guidance on clock tree synthesis and optimization for energy-efficient designs. + Ensure compliance… more
- Cisco (Milpitas, CA)
- …**Your Impact** We are looking for a skilled and proactive FPGA Design Engineer with 3+ years of industry experience to manage and implement complex digital ... high-speed design practices, and debugging on hardware. The Intermediate Engineer is expected to deliver production-quality, optimized designs and contribute… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior SOC Design Engineer to join our SOC Design team! At NVIDIA, you'll collaborate with brilliant minds to build cutting-edge GPUs and ... from AI to gaming! As a Senior SOC Design Engineer , you'll work at the forefront of technology, integrating...technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software, DFT,… more
- Silvus Technologies (Irvine, CA)
- …field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking ... engineers. + RTL coding, simulation, and test bench development. + FPGA synthesis and timing closure. + Hardware verification and troubleshooting; familiarity with… more
- Silvus Technologies (Irvine, CA)
- …field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking ... engineers. + RTL coding, simulation, and test bench development. + FPGA synthesis and timing closure. + Hardware verification and troubleshooting; familiarity with… more
- quadric.io, Inc (Burlingame, CA)
- …architecture by understanding its applications + Own microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilog + Own Power, ... Computer Engineering with a minimum of five years of CPU/GPU/ ASIC front-end design + Proficiency in SystemC, SystemVerilog, or...FPGA design is a plus + Experience in logic synthesis and performance modeling Nice to haves: + Familiarity… more