- Silvus Technologies (Irvine, CA)
- …career._ THE OPPORTUNITY Silvus is seeking a full-time Principal FPGA / RTL Design Engineer who will report to the Senior Engineering Director for Irvine and work ... field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking… more
- Cisco (Milpitas, CA)
- …functionality at the block and system level using simulation tools (eg, VCS). + Synthesis & Implementation : Manage the entire FPGA tool flow, including ... We are seeking a highly experienced and accomplished FPGA Senior Design Engineer to provide technical leadership and deep expertise in the architecture, design,… more
- Cisco (Milpitas, CA)
- …**Your Impact** We are looking for a skilled and proactive FPGA Design Engineer with 3+ years of industry experience to manage and implement complex digital ... high-speed design practices, and debugging on hardware. The Intermediate Engineer is expected to deliver production-quality, optimized designs and contribute… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for a Senior SOC Design Engineer to join our SOC Design team! At NVIDIA, you'll collaborate with brilliant minds to build cutting-edge GPUs and ... from AI to gaming! As a Senior SOC Design Engineer , you'll work at the forefront of technology, integrating...technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software, DFT,… more
- Silvus Technologies (Irvine, CA)
- …field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking ... engineers. + RTL coding, simulation, and test bench development. + FPGA synthesis and timing closure. + Hardware verification and troubleshooting; familiarity with… more
- Silvus Technologies (Irvine, CA)
- …field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking ... engineers. + RTL coding, simulation, and test bench development. + FPGA synthesis and timing closure. + Hardware verification and troubleshooting; familiarity with… more
- quadric.io, Inc (Burlingame, CA)
- …architecture by understanding its applications + Own microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilog + Own Power, ... Computer Engineering with a minimum of five years of CPU/GPU/ ASIC front-end design + Proficiency in SystemC, SystemVerilog, or...FPGA design is a plus + Experience in logic synthesis and performance modeling Nice to haves: + Familiarity… more
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